f4.map.eqn

FPGA光电编码器输入模块

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--inst2 is inst2
inst2 = DFFEAS(inst1, CLK, CLR,  ,  ,  ,  ,  ,  );


--inst4 is inst4
inst4 = DFFEAS(INB, CLK, CLR,  ,  ,  ,  ,  ,  );


--inst5 is inst5
inst5 = DFFEAS(inst, CLK, CLR,  ,  ,  ,  ,  ,  );


--inst6 is inst6
inst6 = DFFEAS(inst4, CLK, CLR,  ,  ,  ,  ,  ,  );


--inst is inst
inst = DFFEAS(INA, CLK, CLR,  ,  ,  ,  ,  ,  );


--A1L13 is inst21~156
A1L13 = inst4 & (inst & (!inst6) # !inst & inst5) # !inst4 & (inst & !inst5 # !inst & (inst6));


--A1L14 is inst22~190
A1L14 = inst6 & (inst5 & (!inst4) # !inst5 & inst) # !inst6 & (inst5 & !inst # !inst5 & (inst4));


--inst26 is inst26
inst26 = !A1L13 & (inst26 # A1L14);


--inst1 is inst1
inst1 = inst4 & inst6 & (inst $ !inst5) # !inst4 & !inst6 & (inst $ !inst5);


--CLK is CLK
--operation mode is input

CLK = INPUT();


--CLR is CLR
--operation mode is input

CLR = INPUT();


--INB is INB
--operation mode is input

INB = INPUT();


--INA is INA
--operation mode is input

INA = INPUT();


--ENADD is ENADD
--operation mode is output

ENADD = OUTPUT(!inst26);


--F4_CLK is F4_CLK
--operation mode is output

F4_CLK = OUTPUT(inst2);