f4.map.rpt

FPGA光电编码器输入模块

; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; -1                 ; -1                 ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                 ;
+----------------------------------+-----------------+------------------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+------------------------------+
; F4.bdf                           ; yes             ; User Block Diagram/Schematic File  ; D:/altera/fpga+dsp/F4/F4.bdf ;
+----------------------------------+-----------------+------------------------------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total combinational functions               ; 4     ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 3     ;
;     -- 3 input functions                    ; 1     ;
;     -- <=2 input functions                  ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 4     ;
;     -- arithmetic mode                      ; 0     ;
; Total registers                             ; 5     ;
; I/O pins                                    ; 6     ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 5     ;
; Total fan-out                               ; 32    ;
; Average fan-out                             ; 2.13  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |F4                        ; 4 (4)             ; 5 (5)        ; 0           ; 0            ; 0       ; 0         ; 6    ; 0            ; |F4                 ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops               ;
+--------------------------------------------------------+---+
; Logic Cell Name                                        ;   ;
+--------------------------------------------------------+---+
; inst26~0                                               ;   ;
; Number of logic cells representing combinational loops ; 1 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 5     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 5     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/altera/fpga+dsp/F4/F4.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Tue Jun 13 16:59:56 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off F4 -c F4
Info: Found 1 design units, including 1 entities, in source file F4.bdf
    Info: Found entity 1: F4
Info: Elaborating entity "F4" for the top level hierarchy
Info: Implemented 14 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 2 output pins
    Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Jun 13 16:59:59 2006
    Info: Elapsed time: 00:00:04