f4.tan.rpt

FPGA光电编码器输入模块

+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+-------+--------+------------+
; Slack ; Required tco ; Actual tco ; From  ; To     ; From Clock ;
+-------+--------------+------------+-------+--------+------------+
; N/A   ; None         ; 9.641 ns   ; inst  ; ENADD  ; CLK        ;
; N/A   ; None         ; 9.580 ns   ; inst6 ; ENADD  ; CLK        ;
; N/A   ; None         ; 9.166 ns   ; inst4 ; ENADD  ; CLK        ;
; N/A   ; None         ; 8.913 ns   ; inst5 ; ENADD  ; CLK        ;
; N/A   ; None         ; 7.636 ns   ; inst2 ; F4_CLK ; CLK        ;
+-------+--------------+------------+-------+--------+------------+


+-------------------------------------------------------------------+
; th                                                                ;
+---------------+-------------+-----------+------+-------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To    ; To Clock ;
+---------------+-------------+-----------+------+-------+----------+
; N/A           ; None        ; -4.035 ns ; INB  ; inst4 ; CLK      ;
; N/A           ; None        ; -4.483 ns ; INA  ; inst  ; CLK      ;
+---------------+-------------+-----------+------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Tue Jun 13 17:00:48 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off F4 -c F4 --timing_analysis_only
Warning: Timing Analysis found one or more latches implemented as combinational loops
    Warning: Node "inst26" is a latch
Info: Found combinational loop of 1 nodes
    Info: Node "inst26"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 340.02 MHz between source register "inst5" and destination register "inst2"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.240 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y13_N13; Fanout = 3; REG Node = 'inst5'
            Info: 2: + IC(0.481 ns) + CELL(0.651 ns) = 1.132 ns; Loc. = LCCOMB_X10_Y13_N8; Fanout = 1; COMB Node = 'inst1'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.240 ns; Loc. = LCFF_X10_Y13_N9; Fanout = 1; REG Node = 'inst2'
            Info: Total cell delay = 0.759 ns ( 61.21 % )
            Info: Total interconnect delay = 0.481 ns ( 38.79 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.803 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(0.854 ns) + CELL(0.666 ns) = 2.803 ns; Loc. = LCFF_X10_Y13_N9; Fanout = 1; REG Node = 'inst2'
                Info: Total cell delay = 1.806 ns ( 64.43 % )
                Info: Total interconnect delay = 0.997 ns ( 35.57 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.803 ns
                Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(0.854 ns) + CELL(0.666 ns) = 2.803 ns; Loc. = LCFF_X10_Y13_N13; Fanout = 3; REG Node = 'inst5'
                Info: Total cell delay = 1.806 ns ( 64.43 % )
                Info: Total interconnect delay = 0.997 ns ( 35.57 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "inst" (data pin = "INA", clock pin = "CLK") is 4.749 ns
    Info: + Longest pin to register delay is 7.592 ns
        Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_180; Fanout = 1; PIN Node = 'INA'
        Info: 2: + IC(6.304 ns) + CELL(0.206 ns) = 7.484 ns; Loc. = LCCOMB_X10_Y13_N24; Fanout = 1; COMB Node = 'inst~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.592 ns; Loc. = LCFF_X10_Y13_N25; Fanout = 4; REG Node = 'inst'
        Info: Total cell delay = 1.288 ns ( 16.97 % )
        Info: Total interconnect delay = 6.304 ns ( 83.03 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.803 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.854 ns) + CELL(0.666 ns) = 2.803 ns; Loc. = LCFF_X10_Y13_N25; Fanout = 4; REG Node = 'inst'
        Info: Total cell delay = 1.806 ns ( 64.43 % )
        Info: Total interconnect delay = 0.997 ns ( 35.57 % )
Info: tco from clock "CLK" to destination pin "ENADD" through register "inst" is 9.641 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.803 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.854 ns) + CELL(0.666 ns) = 2.803 ns; Loc. = LCFF_X10_Y13_N25; Fanout = 4; REG Node = 'inst'
        Info: Total cell delay = 1.806 ns ( 64.43 % )
        Info: Total interconnect delay = 0.997 ns ( 35.57 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 6.534 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y13_N25; Fanout = 4; REG Node = 'inst'
        Info: 2: + IC(0.484 ns) + CELL(0.650 ns) = 1.134 ns; Loc. = LCCOMB_X10_Y13_N12; Fanout = 2; COMB Node = 'inst22~190'
        Info: 3: + IC(0.000 ns) + CELL(1.285 ns) = 2.419 ns; Loc. = LCCOMB_X10_Y13_N26; Fanout = 2; COMB LOOP Node = 'inst26'
            Info: Loc. = LCCOMB_X10_Y13_N26; Node "inst26"
        Info: 4: + IC(0.849 ns) + CELL(3.266 ns) = 6.534 ns; Loc. = PIN_189; Fanout = 0; PIN Node = 'ENADD'
        Info: Total cell delay = 5.201 ns ( 79.60 % )
        Info: Total interconnect delay = 1.333 ns ( 20.40 % )
Info: th for register "inst4" (data pin = "INB", clock pin = "CLK") is -4.035 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.803 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.854 ns) + CELL(0.666 ns) = 2.803 ns; Loc. = LCFF_X10_Y13_N11; Fanout = 4; REG Node = 'inst4'
        Info: Total cell delay = 1.806 ns ( 64.43 % )
        Info: Total interconnect delay = 0.997 ns ( 35.57 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.144 ns
        Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_191; Fanout = 1; PIN Node = 'INB'
        Info: 2: + IC(5.710 ns) + CELL(0.460 ns) = 7.144 ns; Loc. = LCFF_X10_Y13_N11; Fanout = 4; REG Node = 'inst4'
        Info: Total cell delay = 1.434 ns ( 20.07 % )
        Info: Total interconnect delay = 5.710 ns ( 79.93 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Tue Jun 13 17:00:49 2006
    Info: Elapsed time: 00:00:02