pulse_count.tan.qmsg

FPGA光电编码器输入模块

{ "Info" "ITDB_FULL_TCO_RESULT" "F4_CLK PULSE_COUNT\[10\] PULSE_COUNT\[10\]~reg0 7.462 ns register " "Info: tco from clock \"F4_CLK\" to destination pin \"PULSE_COUNT\[10\]\" through register \"PULSE_COUNT\[10\]~reg0\" is 7.462 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F4_CLK source 2.779 ns + Longest register " "Info: + Longest clock path from clock \"F4_CLK\" to source register is 2.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns F4_CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'F4_CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { F4_CLK } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns F4_CLK~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'F4_CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.143 ns" { F4_CLK F4_CLK~clkctrl } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.666 ns) 2.779 ns PULSE_COUNT\[10\]~reg0 3 REG LCFF_X1_Y3_N21 3 " "Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N21; Fanout = 3; REG Node = 'PULSE_COUNT\[10\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "1.496 ns" { F4_CLK~clkctrl PULSE_COUNT[10]~reg0 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.99 % ) " "Info: Total cell delay = 1.806 ns ( 64.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.973 ns ( 35.01 % ) " "Info: Total interconnect delay = 0.973 ns ( 35.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.779 ns" { F4_CLK F4_CLK~clkctrl PULSE_COUNT[10]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.779 ns" { F4_CLK F4_CLK~combout F4_CLK~clkctrl PULSE_COUNT[10]~reg0 } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.379 ns + Longest register pin " "Info: + Longest register to pin delay is 4.379 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PULSE_COUNT\[10\]~reg0 1 REG LCFF_X1_Y3_N21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N21; Fanout = 3; REG Node = 'PULSE_COUNT\[10\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[10]~reg0 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.099 ns) + CELL(3.280 ns) 4.379 ns PULSE_COUNT\[10\] 2 PIN PIN_47 0 " "Info: 2: + IC(1.099 ns) + CELL(3.280 ns) = 4.379 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'PULSE_COUNT\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "4.379 ns" { PULSE_COUNT[10]~reg0 PULSE_COUNT[10] } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.280 ns ( 74.90 % ) " "Info: Total cell delay = 3.280 ns ( 74.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.099 ns ( 25.10 % ) " "Info: Total interconnect delay = 1.099 ns ( 25.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "4.379 ns" { PULSE_COUNT[10]~reg0 PULSE_COUNT[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.379 ns" { PULSE_COUNT[10]~reg0 PULSE_COUNT[10] } { 0.000ns 1.099ns } { 0.000ns 3.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.779 ns" { F4_CLK F4_CLK~clkctrl PULSE_COUNT[10]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.779 ns" { F4_CLK F4_CLK~combout F4_CLK~clkctrl PULSE_COUNT[10]~reg0 } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "4.379 ns" { PULSE_COUNT[10]~reg0 PULSE_COUNT[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.379 ns" { PULSE_COUNT[10]~reg0 PULSE_COUNT[10] } { 0.000ns 1.099ns } { 0.000ns 3.280ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "PULSE_COUNT\[1\]~reg0 DIRECTION F4_CLK 0.094 ns register " "Info: th for register \"PULSE_COUNT\[1\]~reg0\" (data pin = \"DIRECTION\", clock pin = \"F4_CLK\") is 0.094 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F4_CLK destination 2.779 ns + Longest register " "Info: + Longest clock path from clock \"F4_CLK\" to destination register is 2.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns F4_CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'F4_CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { F4_CLK } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns F4_CLK~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'F4_CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.143 ns" { F4_CLK F4_CLK~clkctrl } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.666 ns) 2.779 ns PULSE_COUNT\[1\]~reg0 3 REG LCFF_X1_Y3_N3 3 " "Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N3; Fanout = 3; REG Node = 'PULSE_COUNT\[1\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "1.496 ns" { F4_CLK~clkctrl PULSE_COUNT[1]~reg0 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.99 % ) " "Info: Total cell delay = 1.806 ns ( 64.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.973 ns ( 35.01 % ) " "Info: Total interconnect delay = 0.973 ns ( 35.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.779 ns" { F4_CLK F4_CLK~clkctrl PULSE_COUNT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.779 ns" { F4_CLK F4_CLK~combout F4_CLK~clkctrl PULSE_COUNT[1]~reg0 } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.991 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.991 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns DIRECTION 1 PIN PIN_24 29 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 29; PIN Node = 'DIRECTION'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { DIRECTION } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.130 ns) + CELL(0.623 ns) 2.883 ns PULSE_COUNT\[1\]~244 2 COMB LCCOMB_X1_Y3_N2 1 " "Info: 2: + IC(1.130 ns) + CELL(0.623 ns) = 2.883 ns; Loc. = LCCOMB_X1_Y3_N2; Fanout = 1; COMB Node = 'PULSE_COUNT\[1\]~244'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "1.753 ns" { DIRECTION PULSE_COUNT[1]~244 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.991 ns PULSE_COUNT\[1\]~reg0 3 REG LCFF_X1_Y3_N3 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.991 ns; Loc. = LCFF_X1_Y3_N3; Fanout = 3; REG Node = 'PULSE_COUNT\[1\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.108 ns" { PULSE_COUNT[1]~244 PULSE_COUNT[1]~reg0 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.861 ns ( 62.22 % ) " "Info: Total cell delay = 1.861 ns ( 62.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.130 ns ( 37.78 % ) " "Info: Total interconnect delay = 1.130 ns ( 37.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.991 ns" { DIRECTION PULSE_COUNT[1]~244 PULSE_COUNT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.991 ns" { DIRECTION DIRECTION~combout PULSE_COUNT[1]~244 PULSE_COUNT[1]~reg0 } { 0.000ns 0.000ns 1.130ns 0.000ns } { 0.000ns 1.130ns 0.623ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.779 ns" { F4_CLK F4_CLK~clkctrl PULSE_COUNT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.779 ns" { F4_CLK F4_CLK~combout F4_CLK~clkctrl PULSE_COUNT[1]~reg0 } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.991 ns" { DIRECTION PULSE_COUNT[1]~244 PULSE_COUNT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.991 ns" { DIRECTION DIRECTION~combout PULSE_COUNT[1]~244 PULSE_COUNT[1]~reg0 } { 0.000ns 0.000ns 1.130ns 0.000ns } { 0.000ns 1.130ns 0.623ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 13 16:20:03 2006 " "Info: Processing ended: Tue Jun 13 16:20:03 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}