pulse_count.tan.qmsg

FPGA光电编码器输入模块

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "F4_CLK " "Info: Assuming node \"F4_CLK\" is an undefined clock" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "F4_CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "F4_CLK register PULSE_COUNT\[1\]~reg0 register PULSE_COUNT\[15\]~reg0 286.7 MHz 3.488 ns Internal " "Info: Clock \"F4_CLK\" has Internal fmax of 286.7 MHz between source register \"PULSE_COUNT\[1\]~reg0\" and destination register \"PULSE_COUNT\[15\]~reg0\" (period= 3.488 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.224 ns + Longest register register " "Info: + Longest register to register delay is 3.224 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PULSE_COUNT\[1\]~reg0 1 REG LCFF_X1_Y3_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N3; Fanout = 3; REG Node = 'PULSE_COUNT\[1\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { PULSE_COUNT[1]~reg0 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(0.621 ns) 1.388 ns PULSE_COUNT\[1\]~245 2 COMB LCCOMB_X1_Y3_N2 2 " "Info: 2: + IC(0.767 ns) + CELL(0.621 ns) = 1.388 ns; Loc. = LCCOMB_X1_Y3_N2; Fanout = 2; COMB Node = 'PULSE_COUNT\[1\]~245'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "1.388 ns" { PULSE_COUNT[1]~reg0 PULSE_COUNT[1]~245 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.474 ns PULSE_COUNT\[2\]~247 3 COMB LCCOMB_X1_Y3_N4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.474 ns; Loc. = LCCOMB_X1_Y3_N4; Fanout = 2; COMB Node = 'PULSE_COUNT\[2\]~247'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.086 ns" { PULSE_COUNT[1]~245 PULSE_COUNT[2]~247 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.560 ns PULSE_COUNT\[3\]~249 4 COMB LCCOMB_X1_Y3_N6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.560 ns; Loc. = LCCOMB_X1_Y3_N6; Fanout = 2; COMB Node = 'PULSE_COUNT\[3\]~249'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.086 ns" { PULSE_COUNT[2]~247 PULSE_COUNT[3]~249 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.646 ns PULSE_COUNT\[4\]~251 5 COMB LCCOMB_X1_Y3_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.646 ns; Loc. = LCCOMB_X1_Y3_N8; Fanout = 2; COMB Node = 'PULSE_COUNT\[4\]~251'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.086 ns" { PULSE_COUNT[3]~249 PULSE_COUNT[4]~251 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.732 ns PULSE_COUNT\[5\]~253 6 COMB LCCOMB_X1_Y3_N10 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.732 ns; Loc. = LCCOMB_X1_Y3_N10; Fanout = 2; COMB Node = 'PULSE_COUNT\[5\]~253'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.086 ns" { PULSE_COUNT[4]~251 PULSE_COUNT[5]~253 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.818 ns PULSE_COUNT\[6\]~255 7 COMB LCCOMB_X1_Y3_N12 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.818 ns; Loc. = LCCOMB_X1_Y3_N12; Fanout = 2; COMB Node = 'PULSE_COUNT\[6\]~255'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.086 ns" { PULSE_COUNT[5]~253 PULSE_COUNT[6]~255 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 2.008 ns PULSE_COUNT\[7\]~257 8 COMB LCCOMB_X1_Y3_N14 2 " "Info: 8: + IC(0.000 ns) + CELL(0.190 ns) = 2.008 ns; Loc. = LCCOMB_X1_Y3_N14; Fanout = 2; COMB Node = 'PULSE_COUNT\[7\]~257'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.190 ns" { PULSE_COUNT[6]~255 PULSE_COUNT[7]~257 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.094 ns PULSE_COUNT\[8\]~259 9 COMB LCCOMB_X1_Y3_N16 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.094 ns; Loc. = LCCOMB_X1_Y3_N16; Fanout = 2; COMB Node = 'PULSE_COUNT\[8\]~259'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.086 ns" { PULSE_COUNT[7]~257 PULSE_COUNT[8]~259 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.180 ns PULSE_COUNT\[9\]~261 10 COMB LCCOMB_X1_Y3_N18 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.180 ns; Loc. = LCCOMB_X1_Y3_N18; Fanout = 2; COMB Node = 'PULSE_COUNT\[9\]~261'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.086 ns" { PULSE_COUNT[8]~259 PULSE_COUNT[9]~261 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.266 ns PULSE_COUNT\[10\]~263 11 COMB LCCOMB_X1_Y3_N20 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.266 ns; Loc. = LCCOMB_X1_Y3_N20; Fanout = 2; COMB Node = 'PULSE_COUNT\[10\]~263'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.086 ns" { PULSE_COUNT[9]~261 PULSE_COUNT[10]~263 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.352 ns PULSE_COUNT\[11\]~265 12 COMB LCCOMB_X1_Y3_N22 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.352 ns; Loc. = LCCOMB_X1_Y3_N22; Fanout = 2; COMB Node = 'PULSE_COUNT\[11\]~265'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.086 ns" { PULSE_COUNT[10]~263 PULSE_COUNT[11]~265 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.438 ns PULSE_COUNT\[12\]~267 13 COMB LCCOMB_X1_Y3_N24 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.438 ns; Loc. = LCCOMB_X1_Y3_N24; Fanout = 2; COMB Node = 'PULSE_COUNT\[12\]~267'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.086 ns" { PULSE_COUNT[11]~265 PULSE_COUNT[12]~267 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.524 ns PULSE_COUNT\[13\]~269 14 COMB LCCOMB_X1_Y3_N26 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.524 ns; Loc. = LCCOMB_X1_Y3_N26; Fanout = 2; COMB Node = 'PULSE_COUNT\[13\]~269'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.086 ns" { PULSE_COUNT[12]~267 PULSE_COUNT[13]~269 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.610 ns PULSE_COUNT\[14\]~271 15 COMB LCCOMB_X1_Y3_N28 1 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.610 ns; Loc. = LCCOMB_X1_Y3_N28; Fanout = 1; COMB Node = 'PULSE_COUNT\[14\]~271'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.086 ns" { PULSE_COUNT[13]~269 PULSE_COUNT[14]~271 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 3.116 ns PULSE_COUNT\[15\]~272 16 COMB LCCOMB_X1_Y3_N30 1 " "Info: 16: + IC(0.000 ns) + CELL(0.506 ns) = 3.116 ns; Loc. = LCCOMB_X1_Y3_N30; Fanout = 1; COMB Node = 'PULSE_COUNT\[15\]~272'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.506 ns" { PULSE_COUNT[14]~271 PULSE_COUNT[15]~272 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.224 ns PULSE_COUNT\[15\]~reg0 17 REG LCFF_X1_Y3_N31 2 " "Info: 17: + IC(0.000 ns) + CELL(0.108 ns) = 3.224 ns; Loc. = LCFF_X1_Y3_N31; Fanout = 2; REG Node = 'PULSE_COUNT\[15\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.108 ns" { PULSE_COUNT[15]~272 PULSE_COUNT[15]~reg0 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.457 ns ( 76.21 % ) " "Info: Total cell delay = 2.457 ns ( 76.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.767 ns ( 23.79 % ) " "Info: Total interconnect delay = 0.767 ns ( 23.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "3.224 ns" { PULSE_COUNT[1]~reg0 PULSE_COUNT[1]~245 PULSE_COUNT[2]~247 PULSE_COUNT[3]~249 PULSE_COUNT[4]~251 PULSE_COUNT[5]~253 PULSE_COUNT[6]~255 PULSE_COUNT[7]~257 PULSE_COUNT[8]~259 PULSE_COUNT[9]~261 PULSE_COUNT[10]~263 PULSE_COUNT[11]~265 PULSE_COUNT[12]~267 PULSE_COUNT[13]~269 PULSE_COUNT[14]~271 PULSE_COUNT[15]~272 PULSE_COUNT[15]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.224 ns" { PULSE_COUNT[1]~reg0 PULSE_COUNT[1]~245 PULSE_COUNT[2]~247 PULSE_COUNT[3]~249 PULSE_COUNT[4]~251 PULSE_COUNT[5]~253 PULSE_COUNT[6]~255 PULSE_COUNT[7]~257 PULSE_COUNT[8]~259 PULSE_COUNT[9]~261 PULSE_COUNT[10]~263 PULSE_COUNT[11]~265 PULSE_COUNT[12]~267 PULSE_COUNT[13]~269 PULSE_COUNT[14]~271 PULSE_COUNT[15]~272 PULSE_COUNT[15]~reg0 } { 0.000ns 0.767ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F4_CLK destination 2.779 ns + Shortest register " "Info: + Shortest clock path from clock \"F4_CLK\" to destination register is 2.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns F4_CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'F4_CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { F4_CLK } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns F4_CLK~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'F4_CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.143 ns" { F4_CLK F4_CLK~clkctrl } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.666 ns) 2.779 ns PULSE_COUNT\[15\]~reg0 3 REG LCFF_X1_Y3_N31 2 " "Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N31; Fanout = 2; REG Node = 'PULSE_COUNT\[15\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "1.496 ns" { F4_CLK~clkctrl PULSE_COUNT[15]~reg0 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.99 % ) " "Info: Total cell delay = 1.806 ns ( 64.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.973 ns ( 35.01 % ) " "Info: Total interconnect delay = 0.973 ns ( 35.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.779 ns" { F4_CLK F4_CLK~clkctrl PULSE_COUNT[15]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.779 ns" { F4_CLK F4_CLK~combout F4_CLK~clkctrl PULSE_COUNT[15]~reg0 } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F4_CLK source 2.779 ns - Longest register " "Info: - Longest clock path from clock \"F4_CLK\" to source register is 2.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns F4_CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'F4_CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { F4_CLK } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns F4_CLK~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'F4_CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.143 ns" { F4_CLK F4_CLK~clkctrl } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.666 ns) 2.779 ns PULSE_COUNT\[1\]~reg0 3 REG LCFF_X1_Y3_N3 3 " "Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N3; Fanout = 3; REG Node = 'PULSE_COUNT\[1\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "1.496 ns" { F4_CLK~clkctrl PULSE_COUNT[1]~reg0 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.99 % ) " "Info: Total cell delay = 1.806 ns ( 64.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.973 ns ( 35.01 % ) " "Info: Total interconnect delay = 0.973 ns ( 35.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.779 ns" { F4_CLK F4_CLK~clkctrl PULSE_COUNT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.779 ns" { F4_CLK F4_CLK~combout F4_CLK~clkctrl PULSE_COUNT[1]~reg0 } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.779 ns" { F4_CLK F4_CLK~clkctrl PULSE_COUNT[15]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.779 ns" { F4_CLK F4_CLK~combout F4_CLK~clkctrl PULSE_COUNT[15]~reg0 } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.779 ns" { F4_CLK F4_CLK~clkctrl PULSE_COUNT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.779 ns" { F4_CLK F4_CLK~combout F4_CLK~clkctrl PULSE_COUNT[1]~reg0 } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "3.224 ns" { PULSE_COUNT[1]~reg0 PULSE_COUNT[1]~245 PULSE_COUNT[2]~247 PULSE_COUNT[3]~249 PULSE_COUNT[4]~251 PULSE_COUNT[5]~253 PULSE_COUNT[6]~255 PULSE_COUNT[7]~257 PULSE_COUNT[8]~259 PULSE_COUNT[9]~261 PULSE_COUNT[10]~263 PULSE_COUNT[11]~265 PULSE_COUNT[12]~267 PULSE_COUNT[13]~269 PULSE_COUNT[14]~271 PULSE_COUNT[15]~272 PULSE_COUNT[15]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.224 ns" { PULSE_COUNT[1]~reg0 PULSE_COUNT[1]~245 PULSE_COUNT[2]~247 PULSE_COUNT[3]~249 PULSE_COUNT[4]~251 PULSE_COUNT[5]~253 PULSE_COUNT[6]~255 PULSE_COUNT[7]~257 PULSE_COUNT[8]~259 PULSE_COUNT[9]~261 PULSE_COUNT[10]~263 PULSE_COUNT[11]~265 PULSE_COUNT[12]~267 PULSE_COUNT[13]~269 PULSE_COUNT[14]~271 PULSE_COUNT[15]~272 PULSE_COUNT[15]~reg0 } { 0.000ns 0.767ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.779 ns" { F4_CLK F4_CLK~clkctrl PULSE_COUNT[15]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.779 ns" { F4_CLK F4_CLK~combout F4_CLK~clkctrl PULSE_COUNT[15]~reg0 } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.779 ns" { F4_CLK F4_CLK~clkctrl PULSE_COUNT[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.779 ns" { F4_CLK F4_CLK~combout F4_CLK~clkctrl PULSE_COUNT[1]~reg0 } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "PULSE_COUNT\[0\]~reg0 RESET F4_CLK 4.448 ns register " "Info: tsu for register \"PULSE_COUNT\[0\]~reg0\" (data pin = \"RESET\", clock pin = \"F4_CLK\") is 4.448 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.267 ns + Longest pin register " "Info: + Longest pin to register delay is 7.267 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 0.975 ns RESET 1 PIN PIN_37 16 " "Info: 1: + IC(0.000 ns) + CELL(0.975 ns) = 0.975 ns; Loc. = PIN_37; Fanout = 16; PIN Node = 'RESET'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { RESET } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.632 ns) + CELL(0.660 ns) 7.267 ns PULSE_COUNT\[0\]~reg0 2 REG LCFF_X1_Y3_N1 3 " "Info: 2: + IC(5.632 ns) + CELL(0.660 ns) = 7.267 ns; Loc. = LCFF_X1_Y3_N1; Fanout = 3; REG Node = 'PULSE_COUNT\[0\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "6.292 ns" { RESET PULSE_COUNT[0]~reg0 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.635 ns ( 22.50 % ) " "Info: Total cell delay = 1.635 ns ( 22.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.632 ns ( 77.50 % ) " "Info: Total interconnect delay = 5.632 ns ( 77.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "7.267 ns" { RESET PULSE_COUNT[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.267 ns" { RESET RESET~combout PULSE_COUNT[0]~reg0 } { 0.000ns 0.000ns 5.632ns } { 0.000ns 0.975ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F4_CLK destination 2.779 ns - Shortest register " "Info: - Shortest clock path from clock \"F4_CLK\" to destination register is 2.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns F4_CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'F4_CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "" { F4_CLK } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns F4_CLK~clkctrl 2 COMB CLKCTRL_G2 16 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'F4_CLK~clkctrl'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "0.143 ns" { F4_CLK F4_CLK~clkctrl } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.666 ns) 2.779 ns PULSE_COUNT\[0\]~reg0 3 REG LCFF_X1_Y3_N1 3 " "Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N1; Fanout = 3; REG Node = 'PULSE_COUNT\[0\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "1.496 ns" { F4_CLK~clkctrl PULSE_COUNT[0]~reg0 } "NODE_NAME" } "" } } { "pulse_count.v" "" { Text "D:/altera/fpga+dsp/pusle_count/pulse_count.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.99 % ) " "Info: Total cell delay = 1.806 ns ( 64.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.973 ns ( 35.01 % ) " "Info: Total interconnect delay = 0.973 ns ( 35.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.779 ns" { F4_CLK F4_CLK~clkctrl PULSE_COUNT[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.779 ns" { F4_CLK F4_CLK~combout F4_CLK~clkctrl PULSE_COUNT[0]~reg0 } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "7.267 ns" { RESET PULSE_COUNT[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.267 ns" { RESET RESET~combout PULSE_COUNT[0]~reg0 } { 0.000ns 0.000ns 5.632ns } { 0.000ns 0.975ns 0.660ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "pulse_count" "UNKNOWN" "V1" "D:/altera/fpga+dsp/pusle_count/db/pulse_count.quartus_db" { Floorplan "D:/altera/fpga+dsp/pusle_count/" "" "2.779 ns" { F4_CLK F4_CLK~clkctrl PULSE_COUNT[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.779 ns" { F4_CLK F4_CLK~combout F4_CLK~clkctrl PULSE_COUNT[0]~reg0 } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}