pulse_count.flow.rpt

FPGA光电编码器输入模块

Flow report for pulse_count
Tue Jun 13 16:20:03 2006
Version 5.1 Build 176 10/26/2005 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Flow Summary                                                                 ;
+------------------------------------+-----------------------------------------+
; Flow Status                        ; Successful - Tue Jun 13 16:20:03 2006   ;
; Quartus II Version                 ; 5.1 Build 176 10/26/2005 SJ Web Edition ;
; Revision Name                      ; pulse_count                             ;
; Top-level Entity Name              ; pulse_count                             ;
; Family                             ; Cyclone II                              ;
; Device                             ; EP2C5Q208C8                             ;
; Timing Models                      ; Preliminary                             ;
; Met timing requirements            ; Yes                                     ;
; Total logic elements               ; 16 / 4,608 ( < 1 % )                    ;
; Total registers                    ; 16                                      ;
; Total pins                         ; 19 / 142 ( 13 % )                       ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 0 / 119,808 ( 0 % )                     ;
; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % )                          ;
; Total PLLs                         ; 0 / 2 ( 0 % )                           ;
+------------------------------------+-----------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 06/13/2006 16:19:21 ;
; Main task         ; Compilation         ;
; Revision Name     ; pulse_count         ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:05     ;
; Fitter               ; 00:00:14     ;
; Assembler            ; 00:00:05     ;
; Timing Analyzer      ; 00:00:02     ;
; Total                ; 00:00:26     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off pulse_count -c pulse_count
quartus_fit --read_settings_files=off --write_settings_files=off pulse_count -c pulse_count
quartus_asm --read_settings_files=off --write_settings_files=off pulse_count -c pulse_count
quartus_tan --read_settings_files=off --write_settings_files=off pulse_count -c pulse_count --timing_analysis_only