pulse_count.tan.rpt

FPGA光电编码器输入模块

; N/A           ; None        ; -4.182 ns ; RESET     ; PULSE_COUNT[5]~reg0  ; F4_CLK   ;
; N/A           ; None        ; -4.182 ns ; RESET     ; PULSE_COUNT[6]~reg0  ; F4_CLK   ;
; N/A           ; None        ; -4.182 ns ; RESET     ; PULSE_COUNT[7]~reg0  ; F4_CLK   ;
; N/A           ; None        ; -4.182 ns ; RESET     ; PULSE_COUNT[8]~reg0  ; F4_CLK   ;
; N/A           ; None        ; -4.182 ns ; RESET     ; PULSE_COUNT[9]~reg0  ; F4_CLK   ;
; N/A           ; None        ; -4.182 ns ; RESET     ; PULSE_COUNT[10]~reg0 ; F4_CLK   ;
; N/A           ; None        ; -4.182 ns ; RESET     ; PULSE_COUNT[11]~reg0 ; F4_CLK   ;
; N/A           ; None        ; -4.182 ns ; RESET     ; PULSE_COUNT[12]~reg0 ; F4_CLK   ;
; N/A           ; None        ; -4.182 ns ; RESET     ; PULSE_COUNT[13]~reg0 ; F4_CLK   ;
; N/A           ; None        ; -4.182 ns ; RESET     ; PULSE_COUNT[14]~reg0 ; F4_CLK   ;
; N/A           ; None        ; -4.182 ns ; RESET     ; PULSE_COUNT[15]~reg0 ; F4_CLK   ;
+---------------+-------------+-----------+-----------+----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Tue Jun 13 16:20:02 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pulse_count -c pulse_count --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "F4_CLK" is an undefined clock
Info: Clock "F4_CLK" has Internal fmax of 286.7 MHz between source register "PULSE_COUNT[1]~reg0" and destination register "PULSE_COUNT[15]~reg0" (period= 3.488 ns)
    Info: + Longest register to register delay is 3.224 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N3; Fanout = 3; REG Node = 'PULSE_COUNT[1]~reg0'
        Info: 2: + IC(0.767 ns) + CELL(0.621 ns) = 1.388 ns; Loc. = LCCOMB_X1_Y3_N2; Fanout = 2; COMB Node = 'PULSE_COUNT[1]~245'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.474 ns; Loc. = LCCOMB_X1_Y3_N4; Fanout = 2; COMB Node = 'PULSE_COUNT[2]~247'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.560 ns; Loc. = LCCOMB_X1_Y3_N6; Fanout = 2; COMB Node = 'PULSE_COUNT[3]~249'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.646 ns; Loc. = LCCOMB_X1_Y3_N8; Fanout = 2; COMB Node = 'PULSE_COUNT[4]~251'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.732 ns; Loc. = LCCOMB_X1_Y3_N10; Fanout = 2; COMB Node = 'PULSE_COUNT[5]~253'
        Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.818 ns; Loc. = LCCOMB_X1_Y3_N12; Fanout = 2; COMB Node = 'PULSE_COUNT[6]~255'
        Info: 8: + IC(0.000 ns) + CELL(0.190 ns) = 2.008 ns; Loc. = LCCOMB_X1_Y3_N14; Fanout = 2; COMB Node = 'PULSE_COUNT[7]~257'
        Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.094 ns; Loc. = LCCOMB_X1_Y3_N16; Fanout = 2; COMB Node = 'PULSE_COUNT[8]~259'
        Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.180 ns; Loc. = LCCOMB_X1_Y3_N18; Fanout = 2; COMB Node = 'PULSE_COUNT[9]~261'
        Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.266 ns; Loc. = LCCOMB_X1_Y3_N20; Fanout = 2; COMB Node = 'PULSE_COUNT[10]~263'
        Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.352 ns; Loc. = LCCOMB_X1_Y3_N22; Fanout = 2; COMB Node = 'PULSE_COUNT[11]~265'
        Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.438 ns; Loc. = LCCOMB_X1_Y3_N24; Fanout = 2; COMB Node = 'PULSE_COUNT[12]~267'
        Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.524 ns; Loc. = LCCOMB_X1_Y3_N26; Fanout = 2; COMB Node = 'PULSE_COUNT[13]~269'
        Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.610 ns; Loc. = LCCOMB_X1_Y3_N28; Fanout = 1; COMB Node = 'PULSE_COUNT[14]~271'
        Info: 16: + IC(0.000 ns) + CELL(0.506 ns) = 3.116 ns; Loc. = LCCOMB_X1_Y3_N30; Fanout = 1; COMB Node = 'PULSE_COUNT[15]~272'
        Info: 17: + IC(0.000 ns) + CELL(0.108 ns) = 3.224 ns; Loc. = LCFF_X1_Y3_N31; Fanout = 2; REG Node = 'PULSE_COUNT[15]~reg0'
        Info: Total cell delay = 2.457 ns ( 76.21 % )
        Info: Total interconnect delay = 0.767 ns ( 23.79 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "F4_CLK" to destination register is 2.779 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'F4_CLK'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'F4_CLK~clkctrl'
            Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N31; Fanout = 2; REG Node = 'PULSE_COUNT[15]~reg0'
            Info: Total cell delay = 1.806 ns ( 64.99 % )
            Info: Total interconnect delay = 0.973 ns ( 35.01 % )
        Info: - Longest clock path from clock "F4_CLK" to source register is 2.779 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'F4_CLK'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'F4_CLK~clkctrl'
            Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N3; Fanout = 3; REG Node = 'PULSE_COUNT[1]~reg0'
            Info: Total cell delay = 1.806 ns ( 64.99 % )
            Info: Total interconnect delay = 0.973 ns ( 35.01 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "PULSE_COUNT[0]~reg0" (data pin = "RESET", clock pin = "F4_CLK") is 4.448 ns
    Info: + Longest pin to register delay is 7.267 ns
        Info: 1: + IC(0.000 ns) + CELL(0.975 ns) = 0.975 ns; Loc. = PIN_37; Fanout = 16; PIN Node = 'RESET'
        Info: 2: + IC(5.632 ns) + CELL(0.660 ns) = 7.267 ns; Loc. = LCFF_X1_Y3_N1; Fanout = 3; REG Node = 'PULSE_COUNT[0]~reg0'
        Info: Total cell delay = 1.635 ns ( 22.50 % )
        Info: Total interconnect delay = 5.632 ns ( 77.50 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "F4_CLK" to destination register is 2.779 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'F4_CLK'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'F4_CLK~clkctrl'
        Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N1; Fanout = 3; REG Node = 'PULSE_COUNT[0]~reg0'
        Info: Total cell delay = 1.806 ns ( 64.99 % )
        Info: Total interconnect delay = 0.973 ns ( 35.01 % )
Info: tco from clock "F4_CLK" to destination pin "PULSE_COUNT[10]" through register "PULSE_COUNT[10]~reg0" is 7.462 ns
    Info: + Longest clock path from clock "F4_CLK" to source register is 2.779 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'F4_CLK'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'F4_CLK~clkctrl'
        Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N21; Fanout = 3; REG Node = 'PULSE_COUNT[10]~reg0'
        Info: Total cell delay = 1.806 ns ( 64.99 % )
        Info: Total interconnect delay = 0.973 ns ( 35.01 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 4.379 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N21; Fanout = 3; REG Node = 'PULSE_COUNT[10]~reg0'
        Info: 2: + IC(1.099 ns) + CELL(3.280 ns) = 4.379 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'PULSE_COUNT[10]'
        Info: Total cell delay = 3.280 ns ( 74.90 % )
        Info: Total interconnect delay = 1.099 ns ( 25.10 % )
Info: th for register "PULSE_COUNT[1]~reg0" (data pin = "DIRECTION", clock pin = "F4_CLK") is 0.094 ns
    Info: + Longest clock path from clock "F4_CLK" to destination register is 2.779 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'F4_CLK'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 16; COMB Node = 'F4_CLK~clkctrl'
        Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N3; Fanout = 3; REG Node = 'PULSE_COUNT[1]~reg0'
        Info: Total cell delay = 1.806 ns ( 64.99 % )
        Info: Total interconnect delay = 0.973 ns ( 35.01 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 2.991 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 29; PIN Node = 'DIRECTION'
        Info: 2: + IC(1.130 ns) + CELL(0.623 ns) = 2.883 ns; Loc. = LCCOMB_X1_Y3_N2; Fanout = 1; COMB Node = 'PULSE_COUNT[1]~244'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.991 ns; Loc. = LCFF_X1_Y3_N3; Fanout = 3; REG Node = 'PULSE_COUNT[1]~reg0'
        Info: Total cell delay = 1.861 ns ( 62.22 % )
        Info: Total interconnect delay = 1.130 ns ( 37.78 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Jun 13 16:20:03 2006
    Info: Elapsed time: 00:00:02