dff.vhd

来自「收集的CPLD_FPGA很好的代码」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dff is
	port(a :in std_logic;
			b :in std_logic;
			sel:in std_logic;
			c:out std_logic);
end dff;
architecture rtl of dff is
begin
process(sel,a,b)
begin
	if(sel='0')then
		c<=a;
	else
		c<=b;
	end if;
end process;
end rtl;