coder_decoder_8_3.vhd

来自「收集的CPLD_FPGA很好的代码」· VHDL 代码 · 共 39 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity coder_decoder_8_3 is
	port(a:in std_logic_vector(7 downto 0);
			b:in std_logic_vector(2 downto 0);
			y:out std_logic_vector(7 downto 0);
			q:out std_logic_vector( 2 downto 0));
end coder_decoder_8_3;
architecture behav of coder_decoder_8_3 is
begin
coder8_3:block
begin
	q<="000" when a="11111110" else
		"001" when a="11111101"else
		"010" when a="11111011"else
		"011" when a="11110111"else
		"100" when a="11101111"else
		"101" when a="11011111"else
		"110" when a="10111111"else
		"111" when a="01111111"else
		"XXXXXXXX";
end block coder8_3;
decoder8_3:block
begin
	y<=	"11111110"when b= "000"else
	    "11111101"when b= "001"else
		"11111011"when b= "010"else
		"11110111"when b= "011"else
		"11101111"when b= "100"else
		"11011111"when b= "101"else
		"10111111"when b= "110"else
		"01111111"when b= "111"else
		"XXXXXXXX";
end block decoder8_3;
end behav;