coder8_3.vhd

来自「收集的CPLD_FPGA很好的代码」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity coder8_3 is
	port(sel:in std_logic_vector(7 downto 0);
			q:out std_logic_vector( 2 downto 0));
end coder8_3;
architecture behav of coder8_3 is
begin
	q<="000" when sel="11111110" else
		"001" when sel="11111101"else
		"010" when sel="11111011"else
		"011" when sel="11110111"else
		"100" when sel="11101111"else
		"101" when sel="11011111"else
		"110" when sel="10111111"else
		"111" when sel="01111111"else
		"XXXXXXXX";
end behav;