myand1.vhd

来自「收集的CPLD_FPGA很好的代码」· VHDL 代码 · 共 14 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity myand1 is
port(a,b:in std_logic;
	q :out std_logic);
end myand1;
architecture rtl of myand1 is
begin
q<=a and b;
end rtl;