myrisc.vhd

来自「收集的CPLD_FPGA很好的代码」· VHDL 代码 · 共 41 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package dp16 is
	function add(a:std_logic_vector;
				b:std_logic_vector)
			return std_logic_vector;
end dp16;
package body dp16 is
function add(a:std_logic_vector;
				b:std_logic_vector)
	return std_logic_vector is
variable  tmp:std_logic_vector(15 downto 0);
begin
		tmp:=a+b;
	return tmp;
end add;
end dp16;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.dp16.all;
entity myrisc is
	port(instruction:in std_logic_vector(1 downto 0);
		a:in std_logic_vector(7 downto 0);
		b:in std_logic_vector(7 downto 0);
		c:out std_logic_vector(15 downto 0));
end myrisc;
architecture behav of myrisc is
begin
process(instruction,a,b)
begin
	case instruction is
		when "00"=>c<=add(a,b);
		when others=> c<="0000000000000000";
	end case;
end process;
end behav;