coder8_3_1.vhd

来自「收集的CPLD_FPGA很好的代码」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity coder8_3_1 is
	port(sel:in std_logic_vector(7 downto 0);
			q:out std_logic_vector( 2 downto 0));
end coder8_3_1;
architecture behav of coder8_3_1 is
begin
	with  sel select 
	q<="000" when "11111110" ,
		"001" when "11111101",
		"010" when "11111011",
		"011" when "11110111",
		"100" when "11101111",
		"101" when "11011111",
		"110" when "10111111",
		"111" when "01111111",
		"XXXXXXXX" when others;
end behav;