mux3to1.vhd

来自「收集的CPLD_FPGA很好的代码」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux3to1 is
	port(a ,c:in std_logic;
			b :in std_logic;
			sela,selb:in std_logic;
			q:out std_logic);
end mux3to1;
architecture rtl of mux3to1 is
begin
PROCESS(sela, selb, a, b, c)
BEGIN
IF sela='1' THEN
q <= a;
ELSIF selb='1' THEN
q <= b;
ELSE
q <= c;
END IF;
END PROCESS;
end rtl;