jioujiaoyan1.vhd

来自「收集的CPLD_FPGA很好的代码」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jioujiaoyan1 is
	port(a:in std_logic_vector(7 downto 0);
			q:out std_logic);
end jioujiaoyan1;
architecture rtl of jioujiaoyan1 is
begin
PROCESS(a)
variable tmp:std_logic;
BEGIN
	tmp:='0';
	i:='0';
	while (i < a'high ) loop
		tmp:=tmp xor a(i);
		i:=i+1;
	end loop;
	q<=tmp;
END PROCESS;
end rtl;