voipadpcm.inc

Cypress 的VOIP DEMO 研究VOIP终端的朋友可以研究研究

TABLESIZE:	equ 80

macro PosDiffMinusStep		; 32 CPU cycles
   mov   A, [_iStep + LSB]	; iDiff -= iStep
   sub   [_iDiff + LSB], A
   mov   A, [_iStep + MSB]
   sbb   [_iDiff + MSB], A
   cmp   [_iDiff + MSB], 128   
endm
macro PosDiffMinusStepCmp	; 29 CPU Cycles
   mov   A, [_iDiff + LSB]	; iDiff - iStep?
   sub   A, [_iStep + LSB]
   mov   A, [_iDiff + MSB]
   sbb   A, [_iStep + MSB]
   cmp   A, 128       
endm
macro PosDiffPlusStep		; 32 CPU cycles
   mov   A, [_iStep + LSB]	; iDiff +c= iStep
   adc   [_iDiff + LSB], A 
   mov   A, [_iStep + MSB]
   adc   [_iDiff + MSB], A
   cmp   [_iDiff + MSB], 128
endm 
macro PosDiffPlusStepCmp	; 29 CPUcycles
   mov   A, [_iDiff + LSB]	; iDiff +c iStep?
   adc   A, [_iStep + LSB]
   mov   A, [_iDiff + MSB]
   adc   A, [_iStep + MSB]
   cmp   A, 128   
endm
macro NegDiffPlusStep		; 32CPU cycles
   mov   A, [_iStep + LSB]	; iDiff += iStep
   add   [_iDiff + LSB], A
   mov   A, [_iStep + MSB]
   adc   [_iDiff + MSB], A
   cmp   [_iDiff + MSB], 128   
endm
macro NegDiffPlusStepCmp	; 29 CPU cycles
   mov   A, [_iDiff + LSB]	; iDiff + iStep?
   add   A, [_iStep + LSB]
   mov   A, [_iDiff + MSB]
   adc   A, [_iStep + MSB]
   cmp   A, 128       
endm
macro NegDiffMinusStep		; 32 CPU cycles
   mov   A, [_iStep + LSB]	; iDiff +=1b= iStep
   sbb   [_iDiff + LSB], A
   mov   A, [_iStep + MSB]
   sbb   [_iDiff + MSB], A
   cmp   [_iDiff + MSB], 128
endm 
macro NegDiffMinusStepCmp	; 29 CPU cycles
   mov   A, [_iDiff + LSB]	; iDiff +b iStep?
   sbb   A, [_iStep + LSB]
   mov   A, [_iDiff + MSB]
   sbb   A, [_iStep +MSB]
   cmp   A, 128   
endm
macro ShiftStepRight		; 14 CPU cycles
   asr   [_iStep + MSB]		; iStep /= 2
   rrc   [_iStep + LSB]
endm 
macro IncrementSP		; 30 CPU cycles          
   add   [@0],@1
   cmp   [@0],TABLESIZE
   jc    . + 5
      mov   [@0],(TABLESIZE-1)
   ;skip overrange 
endm
macro DecrementSP		; 20 CPU cycles
   dec   [@0] 
   jnc   . + 5
      mov   [@0],0 
   ;skip underflow
endm

macro   UpdateEncodePos		; 53 CPU cycles
   mov   A, [_bEncStepSizePtr]     ; New Predict Value
   mov   X, A
   index @0 + TABLESIZE
   add   [_iEncPredict + LSB], A
   mov   A, X
   index @0
   adc   [_iEncPredict + MSB], A
endm
macro   UpdateEncodeNeg		; 53 CPU cycles
   mov   A, [_bEncStepSizePtr]     ; New Predict Value
   mov   X, A
   index @0 + TABLESIZE
   sub   [_iEncPredict + LSB], A
   mov   A, X
   index @0
   sbb   [_iEncPredict + MSB], A
endm
macro UpdateDecodePos		; 53 CPU cycles
   mov   A, [_bDecStepSizePtr]     ; New Predict Value
   mov   X, A
   index @0 + TABLESIZE
   add   [_iDecPredict + LSB], A
   mov   A, X
   index @0
   adc   [_iDecPredict + MSB], A
endm
macro UpdateDecodeNeg		; 53 CPU cycles
   mov   A, [_bDecStepSizePtr]      ; New Predict Value
   mov   X, A
   index @0 + TABLESIZE
   sub   [_iDecPredict + LSB], A
   mov   A, X
   index @0
   sbb   [_iDecPredict + MSB], A
endm