operations.s54

TMS320C54系列在CCS3.1 下实验教程

;******************************************************************************
;               		SJTU DSP Tech. Center
;        Copyright (c) 2002 SJTU DSP Tech. Center. All Rights Reserved.
;  History:
;		Date		Authors			Changes
;		2003/09/30	Fu Xuan			Created.
;******************************************************************************
	.mmregs

	.global	_c_int00
	.global _flash_init
	.global	_flash_erase
	.global _flash_address_write
	.global	_flash_data_write
	.global	_flash_version

;------------------------------------------------------------------	
;void flash_init();
;    	C  interface 	
;-----------------------------------------------------------------
_flash_init:
	stm		#0x00e0, PMST		;IPTR=0x0080, MP/MC=1, OVLY=1
	stm		#0x7fff, SWWSR		;software wait state = 7
;	stm		#0x7492, SWWSR		;wait states=2
	stm		#0x0001, 0x002B		;(register SWCR)SWSM=1, wait states are multipled by 2
	stm		#0x8806, BSCR
	ssbx	INTM

	;select flash memory	
	stm		#0x0000, AR2
	portw	*(AR2), 0x0002			;DMCTRL=0x00
	stm		#0x0020, AR2
	portw	*(AR2), 0x0004			;CNTL2=0x20(FLASHENB=1)
	
	stm		#0x0007, AR2
	portw 	*(AR2), 0x0000			;Turn LEDs On
	
	;configure CLKMD to find out the critical frequency
	;PLL mode must be changed to DIV mode before configure a new setting
;	ld 		#0x6ffe, B			;PLLMUL=6(70MHz), PLLDIV=1, PLLCOUNT=255, PLLON/OFF=1, PLLNDIV=1, PLLSTATUS=1
;	ld 		#0x37f6, B
	ld		#0x27f6, B			;PLLMUL=2(60MHz), PLLDIV=0, PLLCOUNT=255, PLLON/OFF=1, PLLNDIV=1, PLLSTATUS=0
set_clk:	
	stm		#0, CLKMD			;shift to DIV mode
test_status:
	ldm		CLKMD, A
	and		#0x0001, A			;test PLLSTATUS bit(0 DIV, 1 PLL)
	bc		test_status, ANEQ
	stlm	B, CLKMD			;after PLL changed to DIV mode, configure the new setting
test_status_1:
	ldm		CLKMD, A
	and		#0x0001, A			;test PLLSTATUS bit(0 DIV, 1 PLL)
	bc		test_status_1, ANEQ
		
	ret
	
;------------------------------------------------------------------	
;int flash_erase();
;		C  interface 	
;-------------------------------------------------------
_flash_erase:				;erase the entire chip  参见文档P8: Table 7
	stm		#0x4555, AR2	
	stm		#0x42AA, AR3

	st 		#0xAA, *AR2		;AA->*(555)
	st 		#0x55, *AR3		;55->*(2AA)
	st 		#0x80, *AR2		;80->*(555)
	st 		#0xAA, *AR2		;AA->*(555)
	st 		#0x55, *AR3		;55->*(2AA)
	st 		#0x10, *AR2		;10->*(555)

	call	wait_completion

	ret
	
;------------------------------------------------------------------	
;int flash_address_write(s16 src_address, s16 dst_address, s16 length);
;		C interface
;	A = src_address
;	push length
;   push dst_address		
;-------------------------------------------------------------
_flash_address_write:		;program	参见文档P8:Table 7
	stm		#0x4555, AR2
	stm		#0x42AA, AR3

	mvdk	*SP(1), AR4		;dst address
	mvdk	*SP(2), AR0		;length
	mar		*AR0-			;循环次数自减1
	stlm	A, AR5			;src address

write:	
	st 		#0xAA, *AR2
	st 		#0x55, *AR3
	st 		#0xA0, *AR2
	
	mvdd	*AR5+, *AR4+	
	
	call	wait_completion

	banz	write, *AR0-
			
	ret
	
;------------------------------------------------------------------	
;int flash_data_write(s16 data, s16 address);
;		C interface
;	A = data
;	push address
;-----------------------------------------------------------------
_flash_data_write:			;program	参见文档P8:Table 7
	stm		#0x4555, AR2
	stm		#0x42AA, AR3

	st 		#0xAA, *AR2		
	st 		#0x55, *AR3
	st 		#0xA0, *AR2
	
	mvdk	*SP(1), AR4		;address
	stl		A, *AR4			;data
	
	call 	wait_completion
	
	ret

;------------------------------------------------------------------	
;void flash_version();
;		C interface
;----------------------------------------------------------------
_flash_version:				;auto select	参见文档P8:Table 7
	stm		#0x4555, AR2
	stm		#0x42AA, AR3

	st 		#0xAA, *AR2
	st 		#0x55, *AR3
	st 		#0x90, *AR2

	ld	    *(0x4000), A	
	ld 		*(0x4001), B
	
	ret

;------------------------------------------------------------------	
wait_completion:
	ld		*(0x4000), A
	ld 		*(0x4000), B
	pshm	AL
	and		#0x0040, A				;extract first DQ6
	and 	#0x0040, B				;extract second DQ6
	xor		B, A					;test whether DQ6 toggle or not
	bcd		end_wait, AEQ			;A=0 when DQ6 do not toggle, Program/Erase complete
	popm	AL 						;to avoid ret to wrong address, pop AL before jump
	nop	
	and		#0x0020, A				;extract DQ5
	bc		wait_completion, AEQ	;wait when DQ5=0(no error occur)
	ld		*(0x4000), A
	and		#0x0040, A
	xor		B, A
	bc		end, ANEQ
;return value A=0 when DQ6 do not toggle, Program/Erase complete
;If Program/Erase error occurs, return value A!=0(0x0040)
end_wait:
	sub		A 						;A=0, Program/Erase complete
end:
	ret
		
;------------------------------------------------------------------	
		.sect	"vectors"
INT_RESET:
	b		_c_int00
	nop
	nop
	
		.space	124*16
			
		.end