convolution1.1.vhd

用汇编语言编写得TD中使用得CC和CRC代码

entity convolution is
  port (inPortmes:in integer32@8;
        inPortsl:in integer16pair@8;
        outPort:out integer32@8);
end entity convolution;
  
architecture C of convolution is
begin STAN2 "-O2"   
  CODE


int main() 
{
   int res_0=0,res_1=0,res_2=0,res_3=0,res_4=0,res_5=0,res_6=0,res_7=0;   // these are used for storing the states of registers.
   int rate2_0,rate2_1;              // when coding rates=1/2, rate2_0,rate2_1 means the two outlets
   int rate3_0,rate3_1,rate3_2;      // when coding rates=1/3, rate3_0,rate3_1,rate3_2 means three outlets
   int store_data,ki,rate,i;         // store_data is used for storing message bit       
   integer32 out;                    
   integer16pair sigling;
   
  while(1)
  {
    sigling = getinPortsl();
    ki = sigling.el1;  		// ki is the length of the message bits
    rate=sigling.el2;             // rate is the coding rate.

    
    for(i=0;i<ki+8;i++)
   {
     switch(rate)                    // judge whether rate=2 or rate=3   
     {  
        case 2:                            //  when rate=2,enter the program from here
	{  if(i<ki)
           {out=getinPortmes();		 // read "ki" message bits
           store_data=(int)out;}
     	   else{store_data=0;}		// add 8 tail bits which are all "0" after the message bits
	   rate2_0=(store_data)^(res_1)^(res_2)^(res_3)^(res_7);
           out=rate2_0;
           putoutPort(out);
	   rate2_1=(store_data)^(res_0)^(res_1)^(res_2)^(res_4)^(res_6)^(res_7);
           out=rate2_1;
           putoutPort(out);
	   res_7=res_6;	
	   res_6=res_5;
	   res_5=res_4;
	   res_4=res_3;  
	   res_3=res_2;
	   res_2=res_1;
	   res_1=res_0;
	   res_0=store_data;    
	   break;
	}
			
        case 3:                    // when RATE=3,enter the program from here
	{  if(i<ki)
           {out=getinPortmes();    // read "ki" message bits
           store_data=(int)out;}   
 	   else{store_data=0;}	// add 8 tail bits which are all "0" after the message bits		
	   rate3_0=(store_data)^(res_1)^(res_2)^(res_4)^(res_5)^(res_6)^(res_7);
           out=rate3_0;
           putoutPort(out);
           rate3_1=(store_data)^(res_0)^(res_2)^(res_3)^(res_6)^(res_7);
           out=rate3_1;
           putoutPort(out);
	   rate3_2=(store_data)^(res_0)^(res_1)^(res_4)^(res_7);
           out=rate3_2;
           putoutPort(out);
	   res_7=res_6;	
	   res_6=res_5;
	   res_5=res_4;
	   res_4=res_3;  
	   res_3=res_2;
	   res_2=res_1;
	   res_1=res_0;
	   res_0=store_data;
           break;
	}
		
          default:
	   break;
       }     // the end of "switch"
		
     }  // the end of "for"
    
 

  }     // the end of "while"
  return 0;
}
  ENDCODE;
end convolution;




library peripherals;
use peripherals.all;

use work.all;

entity convolutionob is
end convolutionob;

architecture STRUCTURAL of convolutionob is

   signal inputmes                         :  integer32@8;
   signal inputsl                          :  integer16pair@8; 
   signal output                           :  integer32@8;  

begin

  convol : entity convolution
  port map(inPortmes  => inputmes,
           inPortsl   => inputsl,
           outPort    => output);

  src0 : entity dataSrc
    generic map (
      sig_t      => integer32,
      fileName   => "inputmes.txt",
      eofDelay   => 100,
      slotRate   => 8,
      debugLevel => 0,
      inputBase => "dec" )
    port map (fileData => inputmes );
  src1 : entity dataSrc
    generic map (
      sig_t      => integer16pair,
      fileName   => "inputsl.txt",
      eofDelay   => 100,
      slotRate   => 8,
      debugLevel => 0,
      inputBase => "dec" )
    port map (fileData => inputsl );

  dst0 : entity dataSink
    generic map (
      sig_t      => integer32,
      fileName   => "output.txt",
      slotRate   => 8,
      debugLevel => 0,
      outputBase => "dec" )
    port map (fileData => output );

end convolutionob;