📄 anticrc.vhd
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entity anticrc is
port (antiCRC_inPortmes:in integer32@8;
antiCRC_inPortsl:in integer32@8;
antiCRC_outPort:out integer32@8;
antiCRC_outPortcheck:out integer32@8);
end entity anticrc;
architecture C of anticrc is
begin STAN2 "-O2"
CODE
int main()
{
unsigned int store_data,bi,li,temp; unsigned int judge,buffer_state,res_state,buffer_state1,res_state1;
integer32 out;
integer32 sigling;
while(1)
{
sigling = getantiCRC_inPortsl();
bi = sigling; // bi is the length of the messages bits(including the CRC) sigling = getantiCRC_inPortsl();
li = sigling; // li is the length of CRC
if(bi==li) // if bi==li,it means that there is no message bits arrived,consider the message bits are correct.let out =1.
{ for(temp=0;temp<li;temp++) out=getantiCRC_inPortmes();
out=1;
putantiCRC_outPortcheck(out);
}
else
{
buffer_state=0;buffer_state1=0;
if(li==8) res_state=435;
if(li==12) res_state=7683;
if(li==16) res_state=2065; if(li==24) { res_state=3; res_state1=396; }
for(temp=0;temp<bi;temp++)
{ if(temp<bi-li)
{
out=getantiCRC_inPortmes();
putantiCRC_outPort(out);
store_data=(int)out;
}
else
{
out=getantiCRC_inPortmes();
store_data=(int)out;
} judge=(store_data)^(buffer_state&1);
if(judge==1)
{
buffer_state^=res_state;
buffer_state>>=1;
if(li==16)
buffer_state^=32768; if(li==24) { buffer_state1^=res_state1; if((buffer_state1&1)==1) {buffer_state|=32768;} buffer_state1>>=1; }
}
else
{
buffer_state>>=1; if(li==24) { if((buffer_state1&1)==1) { buffer_state|=32768;} buffer_state1>>=1; }
}
} // the end of "for"
if((buffer_state==0)&&(buffer_state1==0))
{
out=1; // if all the states of the registers are "0",then the message bits are correct,let out=1.
putantiCRC_outPortcheck(out);
}
else // if any of the states of the registers is not "0",then the message bits are wrong,let out=0.
{
out=0;
putantiCRC_outPortcheck(out);
}
} // the end of "else"
} // the end of "while"
return 0;
}
ENDCODE;
end anticrc;
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