📄 crc.vhd
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entity crc is
port (CRC_inPortmes:in integer32@8;
CRC_inPortsl:in integer32@8;
CRC_outPort:out integer32@8);
end entity crc;
architecture C of crc is
begin STAN2 "-O2"
CODE
int main()
{
unsigned int store_data,ai,li,temp;
unsigned int judge,buffer_state,res_state,buffer_state1,res_state1;
integer32 out;
integer32 sigling;
while(1)
{
sigling = getCRC_inPortsl();
ai = sigling; // ai is the length of the messages bits
sigling = getCRC_inPortsl();
li = sigling; // li is the length of the CRC.
if(ai==0)
{
for(temp=0;temp<li;temp++)
{
out=0; // if ai==0, then all the CRC bits equal to zero.
putCRC_outPort(out);
}
}
else
{
buffer_state=0; buffer_state1=0;
if(li==8) res_state=435;
if(li==12) res_state=7683;
if(li==16) res_state=2065;
if(li==24) { res_state=3; res_state1=396;}
for(temp=0;temp<ai;temp++)
{
out=getCRC_inPortmes();
putCRC_outPort(out);
store_data=(int)out;
judge=(store_data)^(buffer_state&1);
if(judge==1)
{
buffer_state^=res_state;
buffer_state>>=1;
if(li==16)
buffer_state|=32768;
if(li==24)
{
buffer_state1^=res_state1;
if((buffer_state1&1)==1)
{buffer_state|=32768;}
buffer_state1>>=1;
}
}
else
{
buffer_state>>=1;
if(li==24)
{
if((buffer_state1&1)==1)
{ buffer_state|=32768;}
buffer_state1>>=1;
}
}
}
if(li<17)
for(temp=0;temp<li;temp++)
{
out=(buffer_state>>temp)&1;
putCRC_outPort(out);
}
else
{
for(temp=0;temp<16;temp++)
{out=(buffer_state>>temp)&1;
putCRC_outPort(out);}
for(temp=0;temp<8;temp++)
{out=(buffer_state1>>temp)&1;
putCRC_outPort(out);}
}
} // the end of "else"
} // the end of "while"
return 0;
}
ENDCODE;
end crc;
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