disp.vhd

来自「采用MaxPlusII写的一个小时钟程序」· VHDL 代码 · 共 46 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.p_stop_watch.ALL;

ENTITY disp IS
	PORT(secl2:IN STD_ULOGIC_VECTOR( 3 DOWNTO 0);
		secl1:IN STD_ULOGIC_VECTOR( 3 DOWNTO 0);
		sec:IN STD_ULOGIC_VECTOR( 3 DOWNTO 0);
		sec10:IN STD_ULOGIC_VECTOR( 2 DOWNTO 0);
		min:IN STD_ULOGIC_VECTOR( 3 DOWNTO 0);
		min10:IN STD_ULOGIC_VECTOR( 2 DOWNTO 0);
		sysres,clk,dispen:IN STD_ULOGIC;
		segment:OUT STD_ULOGIC_VECTOR(6 DOWNTO 0);
		common: OUT STD_ULOGIC_VECTOR(5 DOWNTO 0));
END disp;

ARCHITECTURE rtl OF disp IS
	SIGNAL selq:STD_ULOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL comcnt_sl:STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL comcnt:STD_ULOGIC_VECTOR(2 DOWNTO 0);
BEGIN
	PROCESS(clk)
		VARIABLE q6: INTEGER;
		BEGIN
			IF (clk'EVENT AND clk='1') THEN
				IF (sysres='1') THEN
					q6:=0;
				ELSIF (dispen='1') THEN
					IF (q6=5) THEN
						q6:=0;
					ELSE
						q6:=q6+1;
					END IF;
				END IF;
			END IF;
		comcnt_sl<=CONV_STD_LOGIC_VECTOR(q6,3);
		comcnt<=TO_STDULOGICVECTOR(comcnt_sl);
	END PROCESS;
selq<=digit_sel(comcnt,min10,min,sec10,sec,secl1,secl2);
segment<=seg_dec(selq);
common<=com_dec(comcnt);
				
END rtl;