📄 clock.rpt
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Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 534
Total flipflops required: 262
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 79/ 576 ( 13%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 4 8 7 8 8 3 8 8 8 8 8 8 0 8 8 8 8 8 8 8 8 8 7 8 8 181/0
B: 8 8 8 8 8 6 8 8 8 8 8 8 0 6 8 8 6 8 7 8 8 8 8 8 8 185/0
C: 8 8 8 8 8 8 8 0 8 0 8 8 0 8 8 8 8 8 8 8 8 8 8 0 8 168/0
Total: 20 24 23 24 24 17 24 16 24 16 24 24 0 22 24 24 22 24 23 24 24 24 23 16 24 534/0
Device-Specific Information: f:\study\vhdl\clock\clock.rpt
clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 CLK
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\study\vhdl\clock\clock.rpt
clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
5 - - - 05 OUTPUT 0 1 0 0 common0
6 - - - 04 OUTPUT 0 1 0 0 common1
7 - - - 03 OUTPUT 0 1 0 0 common2
8 - - - 03 OUTPUT 0 1 0 0 common3
9 - - - 02 OUTPUT 0 1 0 0 common4
10 - - - 01 OUTPUT 0 1 0 0 common5
16 - - A -- OUTPUT 0 1 0 0 segment0
17 - - A -- OUTPUT 0 1 0 0 segment1
18 - - A -- OUTPUT 0 1 0 0 segment2
19 - - A -- OUTPUT 0 1 0 0 segment3
21 - - B -- OUTPUT 0 1 0 0 segment4
22 - - B -- OUTPUT 0 1 0 0 segment5
23 - - B -- OUTPUT 0 1 0 0 segment6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\study\vhdl\clock\clock.rpt
clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - C 06 AND2 0 2 0 1 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:167
- 2 - C 06 AND2 0 4 0 4 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:175
- 3 - C 14 AND2 0 2 0 1 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:179
- 4 - C 15 AND2 0 4 0 4 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:187
- 6 - C 15 AND2 0 2 0 1 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:191
- 8 - C 15 AND2 0 4 0 2 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:199
- 5 - C 13 AND2 0 2 0 3 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:203
- 1 - C 16 AND2 0 3 0 3 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:211
- 2 - C 16 AND2 0 3 0 3 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:219
- 4 - C 24 AND2 0 3 0 3 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:227
- 2 - C 24 AND2 0 3 0 3 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:235
- 3 - C 13 AND2 0 3 0 3 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:243
- 4 - C 13 AND2 0 3 0 4 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:251
- 3 - C 22 AND2 0 2 0 1 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:255
- 2 - C 22 AND2 0 4 0 2 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:263
- 4 - C 22 AND2 0 2 0 3 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:267
- 1 - C 19 AND2 0 3 0 3 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:275
- 5 - C 19 AND2 0 2 0 1 |CNT6:3|LPM_ADD_SUB:196|addcore:adder|:279
- 8 - C 14 DFFE 0 5 0 33 |CNT6:3|ca (|CNT6:3|:8)
- 7 - C 19 DFFE 0 4 0 1 |CNT6:3|q631 (|CNT6:3|:12)
- 4 - C 19 DFFE 0 4 0 2 |CNT6:3|q630 (|CNT6:3|:13)
- 2 - C 19 DFFE 0 3 0 3 |CNT6:3|q629 (|CNT6:3|:14)
- 3 - C 19 DFFE 0 4 0 2 |CNT6:3|q628 (|CNT6:3|:15)
- 8 - C 19 DFFE 0 3 0 3 |CNT6:3|q627 (|CNT6:3|:16)
- 8 - C 22 DFFE 0 3 0 2 |CNT6:3|q626 (|CNT6:3|:17)
- 6 - C 22 DFFE 0 4 0 2 |CNT6:3|q625 (|CNT6:3|:18)
- 7 - C 22 DFFE 0 4 0 3 |CNT6:3|q624 (|CNT6:3|:19)
- 1 - C 22 DFFE 0 3 0 4 |CNT6:3|q623 (|CNT6:3|:20)
- 8 - C 13 DFFE 0 4 0 2 |CNT6:3|q622 (|CNT6:3|:21)
- 6 - C 13 DFFE 0 3 0 3 |CNT6:3|q621 (|CNT6:3|:22)
- 1 - C 13 DFFE 0 4 0 2 |CNT6:3|q620 (|CNT6:3|:23)
- 1 - C 24 DFFE 0 3 0 3 |CNT6:3|q619 (|CNT6:3|:24)
- 8 - C 24 DFFE 0 4 0 2 |CNT6:3|q618 (|CNT6:3|:25)
- 7 - C 24 DFFE 0 3 0 3 |CNT6:3|q617 (|CNT6:3|:26)
- 5 - C 24 DFFE 0 4 0 2 |CNT6:3|q616 (|CNT6:3|:27)
- 3 - C 24 DFFE 0 3 0 3 |CNT6:3|q615 (|CNT6:3|:28)
- 5 - C 16 DFFE 0 4 0 2 |CNT6:3|q614 (|CNT6:3|:29)
- 4 - C 16 DFFE 0 3 0 3 |CNT6:3|q613 (|CNT6:3|:30)
- 3 - C 16 DFFE 0 4 0 2 |CNT6:3|q612 (|CNT6:3|:31)
- 7 - C 16 DFFE 0 3 0 3 |CNT6:3|q611 (|CNT6:3|:32)
- 7 - C 13 DFFE 0 3 0 2 |CNT6:3|q610 (|CNT6:3|:33)
- 7 - C 15 DFFE 0 4 0 2 |CNT6:3|q69 (|CNT6:3|:34)
- 3 - C 15 DFFE 0 4 0 3 |CNT6:3|q68 (|CNT6:3|:35)
- 5 - C 15 DFFE 0 3 0 4 |CNT6:3|q67 (|CNT6:3|:36)
- 2 - C 15 DFFE 0 4 0 2 |CNT6:3|q66 (|CNT6:3|:37)
- 4 - C 14 DFFE 0 4 0 3 |CNT6:3|q65 (|CNT6:3|:38)
- 5 - C 14 DFFE 0 3 0 4 |CNT6:3|q64 (|CNT6:3|:39)
- 5 - C 06 DFFE 0 4 0 2 |CNT6:3|q63 (|CNT6:3|:40)
- 4 - C 06 DFFE 0 4 0 4 |CNT6:3|q62 (|CNT6:3|:41)
- 6 - C 06 DFFE 0 3 0 5 |CNT6:3|q61 (|CNT6:3|:42)
- 7 - C 14 DFFE 0 1 0 7 |CNT6:3|q60 (|CNT6:3|:43)
- 1 - C 15 OR2 s 0 4 0 1 |CNT6:3|~126~1
- 1 - C 06 OR2 s 0 4 0 2 |CNT6:3|~126~2
- 2 - C 13 OR2 s 0 4 0 1 |CNT6:3|~126~3
- 6 - C 24 OR2 s 0 4 0 1 |CNT6:3|~126~4
- 8 - C 16 OR2 s 0 4 0 1 |CNT6:3|~126~5
- 6 - C 16 OR2 s 0 4 0 1 |CNT6:3|~126~6
- 1 - C 14 OR2 s 0 4 0 2 |CNT6:3|~126~7
- 6 - C 19 OR2 s 0 3 0 1 |CNT6:3|~126~8
- 5 - C 22 OR2 s 0 3 0 1 |CNT6:3|~126~9
- 6 - C 14 OR2 s 0 4 0 2 |CNT6:3|~126~10
- 2 - C 14 OR2 ! 0 4 0 31 |CNT6:3|:126
- 4 - A 04 AND2 0 2 0 1 |CNT6:17|LPM_ADD_SUB:196|addcore:adder|:167
- 1 - A 04 AND2 0 4 0 4 |CNT6:17|LPM_ADD_SUB:196|addcore:adder|:175
- 1 - A 10 AND2 0 2 0 1 |CNT6:17|LPM_ADD_SUB:196|addcore:adder|:179
- 4 - A 05 AND2 0 4 0 4 |CNT6:17|LPM_ADD_SUB:196|addcore:adder|:187
- 7 - A 05 AND2 0 2 0 1 |CNT6:17|LPM_ADD_SUB:196|addcore:adder|:191
- 2 - A 05 AND2 0 4 0 2 |CNT6:17|LPM_ADD_SUB:196|addcore:adder|:199
- 4 - A 10 AND2 0 2 0 3 |CNT6:17|LPM_ADD_SUB:196|addcore:adder|:203
- 4 - A 11 AND2 0 3 0 3 |CNT6:17|LPM_ADD_SUB:196|addcore:adder|:211
- 5 - A 11 AND2 0 3 0 3 |CNT6:17|LPM_ADD_SUB:196|addcore:adder|:219
- 1 - A 08 AND2 0 3 0 3 |CNT6:17|LPM_ADD_SUB:196|addcore:adder|:227
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