📄 clock.rpt
字号:
clock
** ERROR SUMMARY **
Info: Chip 'clock' in device 'EPF10K10LC84-4' has less than 20% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
^
C
R R R R R R R O
E c c c c c c E E E E E E N
S o o o o o o V S G G S G S S S S F
E m m m m m m C E N N E N E E E E _ ^
R m m m m m m C R D D R D R R R R # D n
V o o o o o o I V I C I V I V V V V T O C
E n n n n n n N E N L N E N E E E E C N E
D 5 4 3 2 1 0 T D T K T D T D D D D K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | RESERVED
^nCE | 14 72 | RESERVED
#TDI | 15 71 | RESERVED
segment0 | 16 70 | RESERVED
segment1 | 17 69 | RESERVED
segment2 | 18 68 | GNDINT
segment3 | 19 67 | RESERVED
VCCINT | 20 66 | RESERVED
segment4 | 21 65 | RESERVED
segment5 | 22 EPF10K10LC84-4 64 | RESERVED
segment6 | 23 63 | VCCINT
RESERVED | 24 62 | RESERVED
RESERVED | 25 61 | RESERVED
GNDINT | 26 60 | RESERVED
RESERVED | 27 59 | RESERVED
RESERVED | 28 58 | RESERVED
RESERVED | 29 57 | #TMS
RESERVED | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G G G G V G R R R R R R R
C n E E E E E C N N N N C N E E E E E E E
C C S S S S S C D D D D C D S S S S S S S
I O E E E E E I I I I I I I E E E E E E E
N N R R R R R N N N N N N N R R R R R R R
T F V V V V V T T T T T T T V V V V V V V
I E E E E E E E E E E E E
G D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\study\vhdl\clock\clock.rpt
clock
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 4/ 8( 50%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 9/22( 40%)
A2 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
A3 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 6/22( 27%)
A4 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
A5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
A6 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
A7 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
A8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 5/22( 22%)
A9 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 4/22( 18%)
A10 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 12/22( 54%)
A11 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 5/22( 22%)
A12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
A13 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
A14 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
A15 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 4/22( 18%)
A16 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
A17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
A18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
A19 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
A20 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
A21 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 6/22( 27%)
A22 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
A23 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
A24 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
B1 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
B2 8/ 8(100%) 5/ 8( 62%) 3/ 8( 37%) 1/2 0/2 2/22( 9%)
B3 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
B4 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 5/22( 22%)
B5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 2/22( 9%)
B6 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
B8 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
B10 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
B11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
B12 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
B13 6/ 8( 75%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B14 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
B15 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
B16 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
B18 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
B19 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
B20 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
B21 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
B22 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
B23 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
B24 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
C1 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
C2 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
C3 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
C4 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
C5 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
C6 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 9/22( 40%)
C7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
C9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
C11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
C12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
C13 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
C14 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 1/2 0/2 11/22( 50%)
C15 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
C16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
C17 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
C18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
C19 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
C20 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
C21 8/ 8(100%) 5/ 8( 62%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
C22 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
C24 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 13/53 ( 24%)
Total logic cells used: 534/576 ( 92%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.32/4 ( 83%)
Total fan-in: 1773/2304 ( 76%)
Total input pins required: 1
Total input I/O cell registers required: 0
Total output pins required: 13
Total output I/O cell registers required: 0
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