div10.vhd

来自「采用MaxPlusII写的一个小时钟程序」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;


ENTITY div10 IS
	PORT(clk:IN STD_ULOGIC;
		 carry1:OUT STD_ULOGIC
		 );
END div10;

ARCHITECTURE rtl OF div10 IS

	SIGNAL ca:STD_ULOGIC;
		BEGIN
		PROCESS(clk)
			VARIABLE cnt10:INTEGER:=0;
			BEGIN
				IF (clk'EVENT AND clk ='1') THEN
						IF(cnt10=9) THEN
							cnt10:=0;
							ca<='1';
						ELSE
							cnt10:=cnt10+1;
							ca<='0';
						END IF;
				END IF;
				
		END PROCESS;
		carry1<=ca;
END rtl;