cntblk.vhd

来自「采用MaxPlusII写的一个小时钟程序」· VHDL 代码 · 共 39 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY cntblk IS
	PORT(sysres,clk,cnten,res:IN STD_ULOGIC;
		 secl2:OUT STD_ULOGIC_VECTOR(3 DOWNTO 0);
		 secl1:OUT STD_ULOGIC_VECTOR(3 DOWNTO 0);
		 sec:OUT STD_ULOGIC_VECTOR(3 DOWNTO 0);
		 sec10:OUT STD_ULOGIC_VECTOR(2 DOWNTO 0);
		 min:OUT STD_ULOGIC_VECTOR(3 DOWNTO 0);
		 min10:OUT STD_ULOGIC_VECTOR(2 DOWNTO 0));
END cntblk;

ARCHITECTURE rtl OF cntblk IS
	COMPONENT cnt6
		PORT(reset,en,clk:IN STD_ULOGIC;
			 carry1:OUT STD_ULOGIC;
			 q:OUT STD_ULOGIC_VECTOR( 2 DOWNTO 0));
	END COMPONENT;
	COMPONENT cnt10
		PORT(reset,en,clk:IN STD_ULOGIC;
		 	 carry1:OUT STD_ULOGIC;
		 	 q:OUT STD_ULOGIC_VECTOR(3 DOWNTO 0));
	END COMPONENT;
	SIGNAL ca_sl_10,ca_sl,ca_s10:STD_ULOGIC;
	SIGNAL clk_s,cnten_s,res_s:STD_ULOGIC;
	SIGNAL ca_ml,ca_m10,ca_sl_100:STD_ULOGIC;
BEGIN
	res_s<=sysres OR res;
	cnten_s<=cnten;
	u0: cnt10 PORT MAP(res_s,cnten_s,clk,ca_sl_100,secl2);
	u1: cnt10 PORT MAP(res_s,ca_sl_100,clk,ca_sl_10,secl1);
	u2: cnt10 PORT MAP(res_s,ca_sl_10,clk,ca_sl,sec);
	u3: cnt6 PORT MAP(res_s,ca_sl,clk,ca_s10,sec10);
	u4: cnt10 PORT MAP(res_s,ca_s10,clk,ca_ml,min);
	u5: cnt6 PORT MAP(res_s,ca_ml,clk,ca_m10,min10);
END rtl;