cnt40000.vhd

采用MaxPlusII写的一个小时钟程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;


ENTITY cnt40000 IS
	PORT(reset,en,clk:IN STD_ULOGIC;
		 carry1:OUT STD_ULOGIC;
		 q:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END cnt40000;

ARCHITECTURE rtl OF cnt40000 IS
		SIGNAL ca:STD_ULOGIC;
		BEGIN
		PROCESS(clk)
			VARIABLE q40000:INTEGER;
			BEGIN
				IF (clk'EVENT AND clk ='1') THEN
					IF (reset='1') THEN
						q40000:=0;
					ELSIF(en='1') THEN
						IF(q40000=39999) THEN
							q40000:=0;
							ca<='1';
						ELSE
								q40000:=q40000+1;
								ca<='0';
						END IF;
					END IF;
				END IF;
		q<=CONV_STD_LOGIC_VECTOR(q40000,15);
		
		END PROCESS;
		PROCESS(ca,en)
			BEGIN
				carry1<=ca AND en;
				
		  	END PROCESS;
END rtl;