📄 disp.rpt
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Device-Specific Information: f:\study\vhdl\clock\disp.rpt
disp
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 14 AND2 0 2 0 8 |LPM_ADD_SUB:229|addcore:adder|:167
- 3 - B 05 AND2 0 2 0 1 |LPM_ADD_SUB:229|addcore:adder|:171
- 8 - B 05 AND2 0 4 0 3 |LPM_ADD_SUB:229|addcore:adder|:179
- 2 - B 09 AND2 0 3 0 3 |LPM_ADD_SUB:229|addcore:adder|:187
- 4 - B 09 AND2 0 3 0 4 |LPM_ADD_SUB:229|addcore:adder|:195
- 2 - B 07 AND2 0 2 0 1 |LPM_ADD_SUB:229|addcore:adder|:199
- 7 - B 07 AND2 0 4 0 4 |LPM_ADD_SUB:229|addcore:adder|:207
- 3 - B 01 AND2 0 2 0 1 |LPM_ADD_SUB:229|addcore:adder|:211
- 2 - B 12 AND2 0 4 0 4 |LPM_ADD_SUB:229|addcore:adder|:219
- 5 - B 10 AND2 0 2 0 1 |LPM_ADD_SUB:229|addcore:adder|:223
- 1 - B 10 AND2 0 4 0 2 |LPM_ADD_SUB:229|addcore:adder|:231
- 1 - B 03 AND2 0 2 0 3 |LPM_ADD_SUB:229|addcore:adder|:235
- 8 - B 03 AND2 0 3 0 3 |LPM_ADD_SUB:229|addcore:adder|:243
- 1 - B 11 AND2 0 3 0 3 |LPM_ADD_SUB:229|addcore:adder|:251
- 4 - B 11 AND2 0 3 0 3 |LPM_ADD_SUB:229|addcore:adder|:259
- 3 - B 02 AND2 0 3 0 3 |LPM_ADD_SUB:229|addcore:adder|:267
- 1 - B 02 AND2 0 3 0 3 |LPM_ADD_SUB:229|addcore:adder|:275
- 6 - B 08 AND2 0 2 0 1 |LPM_ADD_SUB:229|addcore:adder|:279
- 8 - B 08 DFFE + 2 1 0 2 q631 (:49)
- 7 - B 01 DFFE + 2 1 0 3 q630 (:50)
- 6 - B 01 DFFE + 2 1 0 4 q629 (:51)
- 4 - B 08 DFFE + 2 1 0 3 q628 (:52)
- 7 - B 02 DFFE + 2 1 0 4 q627 (:53)
- 5 - B 02 DFFE + 2 1 0 3 q626 (:54)
- 6 - B 07 DFFE + 2 1 0 4 q625 (:55)
- 2 - B 19 DFFE + 2 1 0 3 q624 (:56)
- 8 - B 11 DFFE + 2 1 0 4 q623 (:57)
- 3 - B 11 DFFE + 2 1 0 3 q622 (:58)
- 3 - B 06 DFFE + 2 1 0 4 q621 (:59)
- 5 - B 03 DFFE + 2 1 0 3 q620 (:60)
- 6 - B 03 DFFE + 2 1 0 4 q619 (:61)
- 2 - B 03 DFFE + 2 1 0 3 q618 (:62)
- 6 - B 10 DFFE + 2 1 0 3 q617 (:63)
- 7 - B 10 DFFE + 2 1 0 4 q616 (:64)
- 3 - B 10 DFFE + 2 1 0 5 q615 (:65)
- 2 - B 06 DFFE + 2 1 0 3 q614 (:66)
- 7 - B 12 DFFE + 2 1 0 4 q613 (:67)
- 8 - B 01 DFFE + 2 1 0 5 q612 (:68)
- 6 - B 12 DFFE + 2 1 0 3 q611 (:69)
- 3 - B 07 DFFE + 2 1 0 4 q610 (:70)
- 4 - B 07 DFFE + 2 1 0 5 q69 (:71)
- 1 - B 04 DFFE + 2 1 0 3 q68 (:72)
- 8 - B 09 DFFE + 2 1 0 4 q67 (:73)
- 6 - B 09 DFFE + 2 1 0 3 q66 (:74)
- 5 - B 05 DFFE + 2 1 0 4 q65 (:75)
- 1 - B 05 DFFE + 2 1 0 3 q64 (:76)
- 2 - B 05 DFFE + 2 1 0 4 q63 (:77)
- 4 - B 06 DFFE + 2 1 0 13 q62 (:78)
- 6 - B 14 DFFE + 2 1 0 7 q61 (:79)
- 4 - B 01 DFFE + 2 0 0 7 q60 (:80)
- 1 - B 12 OR2 s 0 4 0 1 ~161~1
- 3 - B 12 OR2 s 0 4 0 1 ~161~2
- 1 - B 09 OR2 s 0 4 0 1 ~161~3
- 5 - B 12 OR2 s 0 4 0 1 ~161~4
- 2 - B 08 OR2 s 0 4 0 1 ~161~5
- 2 - B 02 OR2 s 0 4 0 1 ~161~6
- 5 - B 11 OR2 s 0 4 0 1 ~161~7
- 3 - B 08 OR2 s 0 4 0 1 ~161~8
- 5 - B 08 OR2 s 0 4 0 1 ~161~9
- 7 - B 08 OR2 0 4 0 1 :438
- 5 - B 01 OR2 0 4 0 1 :450
- 2 - B 01 OR2 0 3 0 1 :459
- 8 - B 02 OR2 0 4 0 1 :468
- 6 - B 02 OR2 0 3 0 1 :477
- 4 - B 02 OR2 0 4 0 1 :486
- 8 - B 07 OR2 0 3 0 1 :495
- 6 - B 11 OR2 0 4 0 1 :504
- 7 - B 11 OR2 0 3 0 1 :513
- 2 - B 11 OR2 0 4 0 1 :522
- 6 - B 06 OR2 0 3 0 1 :531
- 3 - B 03 OR2 0 4 0 1 :540
- 7 - B 03 OR2 0 3 0 1 :549
- 4 - B 03 OR2 0 3 0 1 :558
- 8 - B 10 OR2 0 4 0 1 :567
- 4 - B 10 OR2 0 4 0 1 :576
- 2 - B 10 OR2 0 3 0 1 :585
- 5 - B 06 OR2 0 4 0 1 :594
- 4 - B 12 OR2 0 4 0 1 :603
- 1 - B 01 OR2 0 3 0 1 :612
- 8 - B 12 OR2 0 4 0 1 :621
- 5 - B 07 OR2 0 4 0 1 :630
- 1 - B 07 OR2 0 3 0 1 :639
- 3 - B 09 OR2 0 4 0 1 :648
- 7 - B 09 OR2 0 3 0 1 :657
- 5 - B 09 OR2 0 4 0 1 :666
- 6 - B 05 OR2 0 3 0 1 :675
- 4 - B 05 OR2 0 4 0 1 :684
- 1 - B 08 OR2 s 1 3 0 31 ~693~1
- 7 - B 05 OR2 0 4 0 1 :693
- 7 - B 06 OR2 0 3 0 1 :702
- 4 - B 14 OR2 0 3 0 1 :711
- 7 - B 14 OR2 ! 0 3 1 4 :900
- 2 - B 14 OR2 ! 0 3 1 4 :910
- 1 - B 06 OR2 ! 0 2 1 0 :920
- 1 - B 14 OR2 ! 0 3 1 4 :930
- 3 - C 18 OR2 ! 2 2 0 1 :933
- 8 - B 14 OR2 ! 0 3 1 4 :940
- 4 - C 18 OR2 ! 1 2 0 1 :943
- 5 - B 14 OR2 ! 0 3 1 4 :950
- 2 - C 18 OR2 ! 1 2 0 11 :953
- 5 - C 19 OR2 2 2 0 1 :962
- 6 - C 19 OR2 1 3 0 1 :965
- 7 - C 19 OR2 1 2 0 1 :968
- 8 - C 19 OR2 1 2 0 1 :971
- 2 - C 19 OR2 1 2 0 11 :974
- 5 - C 18 OR2 ! 2 2 0 1 :983
- 6 - C 18 OR2 ! 1 3 0 1 :986
- 7 - C 18 OR2 ! 1 2 0 1 :989
- 8 - C 18 OR2 ! 1 2 0 1 :992
- 1 - C 18 OR2 ! 1 2 0 11 :995
- 3 - C 19 OR2 2 2 0 1 :1004
- 4 - C 19 OR2 1 3 0 1 :1007
- 1 - C 19 OR2 1 2 0 1 :1010
- 2 - C 13 OR2 1 2 0 1 :1013
- 1 - C 13 OR2 1 2 0 9 :1016
- 7 - C 15 OR2 s 0 4 0 1 ~1281~1
- 6 - C 15 OR2 ! 0 4 0 4 :1290
- 2 - C 15 AND2 0 4 0 4 :1302
- 1 - C 15 OR2 0 4 1 0 :1307
- 7 - C 21 OR2 0 3 0 1 :1326
- 2 - C 21 OR2 0 4 1 0 :1338
- 3 - C 15 OR2 0 4 1 0 :1371
- 6 - C 21 OR2 0 4 0 1 :1397
- 1 - C 21 OR2 0 4 1 0 :1404
- 5 - C 15 OR2 0 4 1 0 :1437
- 8 - C 15 OR2 0 4 0 1 :1460
- 4 - C 15 OR2 0 4 1 0 :1470
- 5 - C 21 OR2 0 4 0 1 :1496
- 3 - C 21 AND2 s 0 3 0 3 ~1497~1
- 4 - C 21 OR2 0 4 1 0 :1503
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\study\vhdl\clock\disp.rpt
disp
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 9/ 96( 9%) 38/ 48( 79%) 2/ 48( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 16/ 96( 16%) 0/ 48( 0%) 21/ 48( 43%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 6/24( 25%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\study\vhdl\clock\disp.rpt
disp
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 32 clk
Device-Specific Information: f:\study\vhdl\clock\disp.rpt
disp
** EQUATIONS **
clk : INPUT;
dispen : INPUT;
min0 : INPUT;
min1 : INPUT;
min2 : INPUT;
min3 : INPUT;
min100 : INPUT;
min101 : INPUT;
min102 : INPUT;
secl10 : INPUT;
secl11 : INPUT;
secl12 : INPUT;
secl13 : INPUT;
secl20 : INPUT;
secl21 : INPUT;
secl22 : INPUT;
secl23 : INPUT;
sec0 : INPUT;
sec1 : INPUT;
sec2 : INPUT;
sec3 : INPUT;
sec100 : INPUT;
sec101 : INPUT;
sec102 : INPUT;
sysres : INPUT;
-- Node name is 'common0'
-- Equation name is 'common0', type is output
common0 = _LC5_B14;
-- Node name is 'common1'
-- Equation name is 'common1', type is output
common1 = _LC8_B14;
-- Node name is 'common2'
-- Equation name is 'common2', type is output
common2 = _LC1_B14;
-- Node name is 'common3'
-- Equation name is 'common3', type is output
common3 = _LC1_B6;
-- Node name is 'common4'
-- Equation name is 'common4', type is output
common4 = _LC2_B14;
-- Node name is 'common5'
-- Equation name is 'common5', type is output
common5 = _LC7_B14;
-- Node name is ':80' = 'q60'
-- Equation name is 'q60', location is LC4_B1, type is buried.
q60 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !dispen & q60 & !sysres
# dispen & !q60 & !sysres;
-- Node name is ':79' = 'q61'
-- Equation name is 'q61', location is LC6_B14, type is buried.
q61 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC4_B14 & !sysres
# !dispen & q61 & !sysres;
-- Node name is ':78' = 'q62'
-- Equation name is 'q62', location is LC4_B6, type is buried.
q62 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC7_B6 & !sysres
# !dispen & q62 & !sysres;
-- Node name is ':77' = 'q63'
-- Equation name is 'q63', location is LC2_B5, type is buried.
q63 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC7_B5 & !sysres
# !dispen & q63 & !sysres;
-- Node name is ':76' = 'q64'
-- Equation name is 'q64', location is LC1_B5, type is buried.
q64 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC4_B5 & !sysres
# !dispen & q64 & !sysres;
-- Node name is ':75' = 'q65'
-- Equation name is 'q65', location is LC5_B5, type is buried.
q65 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC6_B5 & !sysres
# !dispen & q65 & !sysres;
-- Node name is ':74' = 'q66'
-- Equation name is 'q66', location is LC6_B9, type is buried.
q66 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC5_B9 & !sysres
# !dispen & q66 & !sysres;
-- Node name is ':73' = 'q67'
-- Equation name is 'q67', location is LC8_B9, type is buried.
q67 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC7_B9 & !sysres
# !dispen & q67 & !sysres;
-- Node name is ':72' = 'q68'
-- Equation name is 'q68', location is LC1_B4, type is buried.
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