cnt6.vhd

来自「采用MaxPlusII写的一个小时钟程序」· VHDL 代码 · 共 41 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY cnt6 IS
	PORT(reset,en,clk:IN STD_ULOGIC;
		 carry1:OUT STD_ULOGIC;
		 q:OUT STD_ULOGIC_VECTOR( 2 DOWNTO 0));
END cnt6;

ARCHITECTURE rtl OF cnt6 IS

	SIGNAL qs:STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL ca:STD_ULOGIC;
		BEGIN
		PROCESS(clk)
			VARIABLE q6:INTEGER;
			BEGIN
				IF (clk'EVENT AND clk ='1') THEN
					IF (reset='1') THEN
						q6:=0;
					ELSIF(en='1') THEN
						IF(q6=5) THEN
							q6:=0;
							ca<='1';
						ELSE
								q6:=q6+1;
								ca<='0';
						END IF;
					END IF;
				END IF;
		qs<=CONV_STD_LOGIC_VECTOR(q6,3);
		q<=TO_STDULOGICVECTOR(qs);
		END PROCESS;
		PROCESS(ca,en)
			BEGIN
				carry1<=ca AND en;
		END PROCESS;
END rtl;