cnt40000.rpt

采用MaxPlusII写的一个小时钟程序

-- Node name is ':450' 
-- Equation name is '_LC3_C22', type is buried 
_LC3_C22 = LCELL( _EQ063);
  _EQ063 =  _LC8_C22 & !q4000029 &  q4000030
         # !_LC2_C24 &  _LC8_C22 &  q4000030
         #  _LC2_C24 &  _LC8_C22 &  q4000029 & !q4000030;

-- Node name is ':459' 
-- Equation name is '_LC2_C22', type is buried 
_LC2_C22 = LCELL( _EQ064);
  _EQ064 = !_LC2_C24 &  _LC8_C22 &  q4000029
         #  _LC2_C24 &  _LC8_C22 & !q4000029;

-- Node name is ':468' 
-- Equation name is '_LC3_C24', type is buried 
_LC3_C24 = LCELL( _EQ065);
  _EQ065 =  _LC8_C22 & !q4000027 &  q4000028
         # !_LC1_C24 &  _LC8_C22 &  q4000028
         #  _LC1_C24 &  _LC8_C22 &  q4000027 & !q4000028;

-- Node name is ':477' 
-- Equation name is '_LC8_C24', type is buried 
_LC8_C24 = LCELL( _EQ066);
  _EQ066 = !_LC1_C24 &  _LC8_C22 &  q4000027
         #  _LC1_C24 &  _LC8_C22 & !q4000027;

-- Node name is ':486' 
-- Equation name is '_LC4_C24', type is buried 
_LC4_C24 = LCELL( _EQ067);
  _EQ067 = !_LC1_C17 &  _LC8_C22 &  q4000026
         #  _LC1_C17 &  _LC8_C22 & !q4000026;

-- Node name is ':495' 
-- Equation name is '_LC6_C17', type is buried 
_LC6_C17 = LCELL( _EQ068);
  _EQ068 =  _LC8_C22 & !q4000024 &  q4000025
         # !_LC4_C17 &  _LC8_C22 &  q4000025
         #  _LC4_C17 &  _LC8_C22 &  q4000024 & !q4000025;

-- Node name is ':504' 
-- Equation name is '_LC3_C17', type is buried 
_LC3_C17 = LCELL( _EQ069);
  _EQ069 =  _LC8_C22 & !q4000023 &  q4000024
         # !_LC4_C23 &  _LC8_C22 &  q4000024
         #  _LC4_C23 &  _LC8_C22 &  q4000023 & !q4000024;

-- Node name is ':513' 
-- Equation name is '_LC7_C17', type is buried 
_LC7_C17 = LCELL( _EQ070);
  _EQ070 = !_LC4_C23 &  _LC8_C22 &  q4000023
         #  _LC4_C23 &  _LC8_C22 & !q4000023;

-- Node name is ':522' 
-- Equation name is '_LC6_C23', type is buried 
_LC6_C23 = LCELL( _EQ071);
  _EQ071 =  _LC8_C22 & !q4000021 &  q4000022
         # !_LC5_C23 &  _LC8_C22 &  q4000022
         #  _LC5_C23 &  _LC8_C22 &  q4000021 & !q4000022;

-- Node name is ':531' 
-- Equation name is '_LC2_C23', type is buried 
_LC2_C23 = LCELL( _EQ072);
  _EQ072 =  _LC8_C22 & !q4000020 &  q4000021
         # !_LC4_C21 &  _LC8_C22 &  q4000021
         #  _LC4_C21 &  _LC8_C22 &  q4000020 & !q4000021;

-- Node name is ':540' 
-- Equation name is '_LC2_C20', type is buried 
_LC2_C20 = LCELL( _EQ073);
  _EQ073 = !_LC4_C21 &  _LC8_C22 &  q4000020
         #  _LC4_C21 &  _LC8_C22 & !q4000020;

-- Node name is ':549' 
-- Equation name is '_LC3_C4', type is buried 
_LC3_C4  = LCELL( _EQ074);
  _EQ074 =  _LC8_C22 & !q4000018 &  q4000019
         # !_LC8_C21 &  _LC8_C22 &  q4000019
         #  _LC8_C21 &  _LC8_C22 &  q4000018 & !q4000019;

-- Node name is ':558' 
-- Equation name is '_LC5_C21', type is buried 
_LC5_C21 = LCELL( _EQ075);
  _EQ075 =  _LC8_C22 & !q4000017 &  q4000018
         # !_LC2_C15 &  _LC8_C22 &  q4000018
         #  _LC2_C15 &  _LC8_C22 &  q4000017 & !q4000018;

-- Node name is ':567' 
-- Equation name is '_LC1_C21', type is buried 
_LC1_C21 = LCELL( _EQ076);
  _EQ076 = !_LC2_C15 &  _LC8_C22 &  q4000017
         #  _LC2_C15 &  _LC8_C22 & !q4000017;

-- Node name is ':576' 
-- Equation name is '_LC3_C15', type is buried 
_LC3_C15 = LCELL( _EQ077);
  _EQ077 =  _LC8_C22 & !q4000015 &  q4000016
         # !_LC1_C15 &  _LC8_C22 &  q4000016
         #  _LC1_C15 &  _LC8_C22 &  q4000015 & !q4000016;

-- Node name is '~585~1' 
-- Equation name is '~585~1', location is LC8_C22, type is buried.
-- synthesized logic cell 
_LC8_C22 = LCELL( _EQ078);
  _EQ078 =  en & !_LC1_C18;

-- Node name is ':585' 
-- Equation name is '_LC4_C15', type is buried 
_LC4_C15 = LCELL( _EQ079);
  _EQ079 = !_LC1_C15 &  _LC8_C22 &  q4000015
         #  _LC1_C15 &  _LC8_C22 & !q4000015;

-- Node name is ':594' 
-- Equation name is '_LC7_C14', type is buried 
_LC7_C14 = LCELL( _EQ080);
  _EQ080 =  en & !_LC1_C18 & !_LC5_C14 &  q4000014
         #  en & !_LC1_C18 &  _LC5_C14 & !q4000014;

-- Node name is ':603' 
-- Equation name is '_LC3_C14', type is buried 
_LC3_C14 = LCELL( _EQ081);
  _EQ081 =  _LC8_C22 & !q4000012 &  q4000013
         # !_LC7_C16 &  _LC8_C22 &  q4000013
         #  _LC7_C16 &  _LC8_C22 &  q4000012 & !q4000013;

-- Node name is ':612' 
-- Equation name is '_LC2_C14', type is buried 
_LC2_C14 = LCELL( _EQ082);
  _EQ082 = !_LC7_C16 &  _LC8_C22 &  q4000012
         #  _LC7_C16 &  _LC8_C22 & !q4000012;

-- Node name is ':621' 
-- Equation name is '_LC8_C16', type is buried 
_LC8_C16 = LCELL( _EQ083);
  _EQ083 = !_LC6_C16 &  _LC8_C22 &  q4000011
         #  _LC6_C16 &  _LC8_C22 & !q4000011;

-- Node name is ':630' 
-- Equation name is '_LC5_C16', type is buried 
_LC5_C16 = LCELL( _EQ084);
  _EQ084 =  _LC8_C22 & !q400009 &  q4000010
         # !_LC6_C19 &  _LC8_C22 &  q4000010
         #  _LC6_C19 &  _LC8_C22 &  q400009 & !q4000010;

-- Node name is ':639' 
-- Equation name is '_LC4_C16', type is buried 
_LC4_C16 = LCELL( _EQ085);
  _EQ085 = !_LC6_C19 &  _LC8_C22 &  q400009
         #  _LC6_C19 &  _LC8_C22 & !q400009;

-- Node name is ':648' 
-- Equation name is '_LC8_C19', type is buried 
_LC8_C19 = LCELL( _EQ086);
  _EQ086 = !_LC7_C19 &  _LC8_C22 &  q400008
         #  _LC7_C19 &  _LC8_C22 & !q400008;

-- Node name is ':657' 
-- Equation name is '_LC4_C19', type is buried 
_LC4_C19 = LCELL( _EQ087);
  _EQ087 =  _LC8_C22 & !q400006 &  q400007
         # !_LC3_C1 &  _LC8_C22 &  q400007
         #  _LC3_C1 &  _LC8_C22 &  q400006 & !q400007;

-- Node name is ':666' 
-- Equation name is '_LC2_C19', type is buried 
_LC2_C19 = LCELL( _EQ088);
  _EQ088 = !_LC3_C1 &  _LC8_C22 &  q400006
         #  _LC3_C1 &  _LC8_C22 & !q400006;

-- Node name is ':675' 
-- Equation name is '_LC8_C1', type is buried 
_LC8_C1  = LCELL( _EQ089);
  _EQ089 =  _LC8_C22 & !q400004 &  q400005
         # !_LC2_C1 &  _LC8_C22 &  q400005
         #  _LC2_C1 &  _LC8_C22 &  q400004 & !q400005;

-- Node name is ':684' 
-- Equation name is '_LC6_C1', type is buried 
_LC6_C1  = LCELL( _EQ090);
  _EQ090 = !_LC2_C1 &  _LC8_C22 &  q400004
         #  _LC2_C1 &  _LC8_C22 & !q400004;

-- Node name is ':693' 
-- Equation name is '_LC8_C4', type is buried 
_LC8_C4  = LCELL( _EQ091);
  _EQ091 = !_LC7_C4 &  _LC8_C22 &  q400003
         #  _LC7_C4 &  _LC8_C22 & !q400003;

-- Node name is ':702' 
-- Equation name is '_LC4_C1', type is buried 
_LC4_C1  = LCELL( _EQ092);
  _EQ092 =  _LC8_C22 & !q400001 &  q400002
         #  _LC8_C22 & !q400000 &  q400002
         #  _LC8_C22 &  q400000 &  q400001 & !q400002;

-- Node name is ':711' 
-- Equation name is '_LC5_C4', type is buried 
_LC5_C4  = LCELL( _EQ093);
  _EQ093 =  _LC8_C22 & !q400000 &  q400001
         #  _LC8_C22 &  q400000 & !q400001;

-- Node name is ':822' 
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _EQ094);
  _EQ094 =  ca &  en;



Project Information                           f:\study\vhdl\clock\cnt40000.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,547K