clkgen.vhd

来自「采用MaxPlusII写的一个小时钟程序」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY clkgen IS
	PORT(sysres,en1,clk:IN STD_ULOGIC;
		 cntclk,keyclk:OUT STD_ULOGIC);
END clkgen;

ARCHITECTURE rtl OF clkgen IS 
	COMPONENT cnt10
		PORT( reset:IN STD_ULOGIC;
			  en:IN STD_ULOGIC;
			  clk:IN STD_ULOGIC;
				carry1:OUT STD_ULOGIC;
				q:OUT STD_ULOGIC_VECTOR(3 DOWNTO 0) );
	END COMPONENT;
	COMPONENT cnt4
		PORT(reset,en,clk:IN STD_ULOGIC;
				carry1:OUT STD_ULOGIC;
				q:OUT STD_ULOGIC_VECTOR(1 DOWNTO 0));
	END COMPONENT;
	SIGNAL cntclk_s:STD_ULOGIC;
BEGIN
	u0:cnt10 PORT MAP(sysres,en1,clk,cntclk_s);
	u1:cnt4 PORT MAP(sysres,cntclk_s,clk,keyclk);
	cntclk<=cntclk_s;
END rtl;