📄 cnt10.rpt
字号:
-- Equation name is '_LC6_C5', type is buried
_LC6_C5 = LCELL( _EQ066);
_EQ066 = _LC4_C2 & !q1027 & q1028
# _LC4_C2 & !_LC5_C5 & q1028
# _LC4_C2 & _LC5_C5 & q1027 & !q1028;
-- Node name is ':467'
-- Equation name is '_LC8_C5', type is buried
_LC8_C5 = LCELL( _EQ067);
_EQ067 = _LC4_C2 & !_LC5_C5 & q1027
# _LC4_C2 & _LC5_C5 & !q1027;
-- Node name is ':476'
-- Equation name is '_LC7_C5', type is buried
_LC7_C5 = LCELL( _EQ068);
_EQ068 = !_LC1_C3 & _LC4_C2 & q1026
# _LC1_C3 & _LC4_C2 & !q1026;
-- Node name is ':485'
-- Equation name is '_LC8_C3', type is buried
_LC8_C3 = LCELL( _EQ069);
_EQ069 = _LC4_C2 & !q1024 & q1025
# _LC4_C2 & !_LC7_C3 & q1025
# _LC4_C2 & _LC7_C3 & q1024 & !q1025;
-- Node name is ':494'
-- Equation name is '_LC6_C3', type is buried
_LC6_C3 = LCELL( _EQ070);
_EQ070 = _LC4_C2 & !q1023 & q1024
# _LC4_C2 & !_LC7_A7 & q1024
# _LC4_C2 & _LC7_A7 & q1023 & !q1024;
-- Node name is ':503'
-- Equation name is '_LC2_C3', type is buried
_LC2_C3 = LCELL( _EQ071);
_EQ071 = _LC4_C2 & !_LC7_A7 & q1023
# _LC4_C2 & _LC7_A7 & !q1023;
-- Node name is ':512'
-- Equation name is '_LC5_A7', type is buried
_LC5_A7 = LCELL( _EQ072);
_EQ072 = _LC4_C2 & !q1021 & q1022
# !_LC1_A7 & _LC4_C2 & q1022
# _LC1_A7 & _LC4_C2 & q1021 & !q1022;
-- Node name is ':521'
-- Equation name is '_LC3_A7', type is buried
_LC3_A7 = LCELL( _EQ073);
_EQ073 = !_LC1_A7 & _LC4_C2 & q1021
# _LC1_A7 & _LC4_C2 & !q1021;
-- Node name is ':530'
-- Equation name is '_LC6_A3', type is buried
_LC6_A3 = LCELL( _EQ074);
_EQ074 = _LC4_C2 & !q1019 & q1020
# _LC4_C2 & !_LC8_A12 & q1020
# _LC4_C2 & _LC8_A12 & q1019 & !q1020;
-- Node name is ':539'
-- Equation name is '_LC7_A3', type is buried
_LC7_A3 = LCELL( _EQ075);
_EQ075 = _LC4_C2 & !_LC8_A12 & q1019
# _LC4_C2 & _LC8_A12 & !q1019;
-- Node name is ':548'
-- Equation name is '_LC5_A12', type is buried
_LC5_A12 = LCELL( _EQ076);
_EQ076 = _LC4_C2 & !q1017 & q1018
# !_LC1_A12 & _LC4_C2 & q1018
# _LC1_A12 & _LC4_C2 & q1017 & !q1018;
-- Node name is ':557'
-- Equation name is '_LC6_A12', type is buried
_LC6_A12 = LCELL( _EQ077);
_EQ077 = !_LC1_A12 & _LC4_C2 & q1017
# _LC1_A12 & _LC4_C2 & !q1017;
-- Node name is ':566'
-- Equation name is '_LC2_A12', type is buried
_LC2_A12 = LCELL( _EQ078);
_EQ078 = _LC4_C2 & !q1015 & q1016
# _LC4_C2 & !_LC8_A8 & q1016
# _LC4_C2 & _LC8_A8 & q1015 & !q1016;
-- Node name is ':575'
-- Equation name is '_LC7_A8', type is buried
_LC7_A8 = LCELL( _EQ079);
_EQ079 = _LC4_C2 & !_LC8_A8 & q1015
# _LC4_C2 & _LC8_A8 & !q1015;
-- Node name is ':584'
-- Equation name is '_LC4_A8', type is buried
_LC4_A8 = LCELL( _EQ080);
_EQ080 = _LC4_C2 & !q1013 & q1014
# _LC4_C2 & !_LC8_A11 & q1014
# _LC4_C2 & _LC8_A11 & q1013 & !q1014;
-- Node name is ':593'
-- Equation name is '_LC2_A8', type is buried
_LC2_A8 = LCELL( _EQ081);
_EQ081 = _LC4_C2 & !_LC8_A11 & q1013
# _LC4_C2 & _LC8_A11 & !q1013;
-- Node name is ':602'
-- Equation name is '_LC3_A11', type is buried
_LC3_A11 = LCELL( _EQ082);
_EQ082 = _LC4_C2 & !q1011 & q1012
# !_LC1_A4 & _LC4_C2 & q1012
# _LC1_A4 & _LC4_C2 & q1011 & !q1012;
-- Node name is ':611'
-- Equation name is '_LC4_A11', type is buried
_LC4_A11 = LCELL( _EQ083);
_EQ083 = !_LC1_A4 & _LC4_C2 & q1011
# _LC1_A4 & _LC4_C2 & !q1011;
-- Node name is ':620'
-- Equation name is '_LC7_A4', type is buried
_LC7_A4 = LCELL( _EQ084);
_EQ084 = !_LC3_A4 & _LC4_C2 & q1010
# _LC3_A4 & _LC4_C2 & !q1010;
-- Node name is ':629'
-- Equation name is '_LC5_A4', type is buried
_LC5_A4 = LCELL( _EQ085);
_EQ085 = _LC4_C2 & !q108 & q109
# !_LC4_A4 & _LC4_C2 & q109
# _LC4_A4 & _LC4_C2 & q108 & !q109;
-- Node name is ':638'
-- Equation name is '_LC8_A3', type is buried
_LC8_A3 = LCELL( _EQ086);
_EQ086 = _LC4_C2 & !q107 & q108
# !_LC2_C1 & _LC4_C2 & q108
# _LC2_C1 & _LC4_C2 & q107 & !q108;
-- Node name is ':647'
-- Equation name is '_LC1_A3', type is buried
_LC1_A3 = LCELL( _EQ087);
_EQ087 = !_LC2_C1 & _LC4_C2 & q107
# _LC2_C1 & _LC4_C2 & !q107;
-- Node name is ':656'
-- Equation name is '_LC6_C1', type is buried
_LC6_C1 = LCELL( _EQ088);
_EQ088 = _LC4_C2 & !q105 & q106
# _LC4_C2 & !_LC5_C1 & q106
# _LC4_C2 & _LC5_C1 & q105 & !q106;
-- Node name is ':665'
-- Equation name is '_LC3_C1', type is buried
_LC3_C1 = LCELL( _EQ089);
_EQ089 = _LC4_C2 & !q104 & q105
# !_LC1_C1 & _LC4_C2 & q105
# _LC1_C1 & _LC4_C2 & q104 & !q105;
-- Node name is '~674~1'
-- Equation name is '~674~1', location is LC4_C2, type is buried.
-- synthesized logic cell
_LC4_C2 = LCELL( _EQ090);
_EQ090 = en & !q100
# en & _LC1_C12;
-- Node name is ':674'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = LCELL( _EQ091);
_EQ091 = _LC4_C2 & !q103 & q104
# !_LC3_C2 & _LC4_C2 & q104
# _LC3_C2 & _LC4_C2 & q103 & !q104;
-- Node name is ':683'
-- Equation name is '_LC8_C7', type is buried
_LC8_C7 = LCELL( _EQ092);
_EQ092 = !_LC3_C2 & _LC4_C2 & q103
# _LC3_C2 & _LC4_C2 & !q103;
-- Node name is ':692'
-- Equation name is '_LC8_C2', type is buried
_LC8_C2 = LCELL( _EQ093);
_EQ093 = _LC4_C2 & !q101 & q102
# _LC4_C2 & !q100 & q102
# _LC4_C2 & q100 & q101 & !q102;
-- Node name is ':701'
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = LCELL( _EQ094);
_EQ094 = _LC4_C2 & !q100 & q101
# _LC4_C2 & q100 & !q101;
-- Node name is ':795'
-- Equation name is '_LC1_A11', type is buried
_LC1_A11 = LCELL( _EQ095);
_EQ095 = ca & en;
Project Information f:\study\vhdl\clock\cnt10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,131K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -