80867100.pci

windwos环境下查看PCI驱动信息的源代码。

%! Detailed register description file for PCICFG.EXE by Ralf Brown
%!
%! Filename 80867100.PCI = Vendor 8086h, Device 7100h
%!    Intel 82439TX System Controller
%! Created 31 Dec 97 by Andy Sawyer
%! Last edit 10jan99 by Ralf Brown
%!
%! Reference : Intel document 29055901.PDF
%! "Intel 430TX PCISET : 82439TX System Controller (MTXC)"
%!

!begin
82439TX System Controller registers in detail:		       [by Andy Sawyer]

 Extended CPU-to-PIIX4 PHLDA# Signalling: %[4F:7]ed
 PCI Concurrency Enable:                  %[50:3]ed
 ACPI Control Register:                   %[79:6]ed
 Suspend Refresh Type :                   %[79:5]|CBR Refresh;Self Refresh|
 Normal Refresh Enable:                   %[79:4]y
 Internal Clock Control:                  %[79:2]ed

 Cache Control:
   Seconday Cache Size:           %[52:7-6]|Not Populated;256K;512K;Reserved|
   L2 SRAM Type:                  %[52:5-4]|Pipelined Burst SRAM;Reserved;Reserved;Two banks of pipelined burst SRAM|
   NA Disable:                    NA is %[52:3]Ed
   Secondary Cache Force Miss:    %[52:1]y
   First Level Cache Enable:      %[52:0]ed
   DRAM Cache L2 present:         %[53:5]y
   DRAM Cache L2 refresh timer:   %[53:4-0]d

 SDRAM Control:
   Special SDRAM mode select:     %[54:8-6](SDMS)
   RAS# to CAS# Override:         %[54:5]ed
   CAS# Latency:                  %[54:4]{23}
   RAS# Timing:                   %[54:3]|3/5/8;3/4/7|
   64-MBit Technology Enable:     %[54:1]y

 DRAM Control:
   Refresh RAS# Assertion:        %[56:6]{45} Clocks
   Fast EDO Lead Off:             %[56:5]ed
   Speculative Lead Off:          %[56:4]Ed
   Memory Address Drive Strength: %[56:2]|10;16|ma %[56:1]|10;16|ma
   Memory Hole:                   %[57:7-6]|none;512K-640K;15M-16M;14M-16M|
   Enhanced Paging:               %[57:4]ed
   Detect Mode:                   %[57:3]ed
   Refresh Rate:                  %[57:2-0]|disabled;15.6;31.2;64.4;125;256;Reserved|
 DRAM Timing:
   Read Burst Timing:             %[58:6-5]|x444/x444;x333/x444;x222/x333;Reserved|
   Write Burst Timing:            %[58:4-3]|x444;x333;x222;Reserved|
   Leadoff Timing:                Read  %[58:0]|11;10|  Write %[58:0]{76}
                                  RAS# Precharge %[58:1]{34}
                                  RAS-to-CAS Delay %[58:0]{43}
  DRAM Boundaries:     %[60]3dM %[61]3dM %[62]3dM
                       %[63]3dM %[64]3dM %[65]3dM
  DRAM Row Type:
     Host Frequency:   %[67:7]|60;66|MHz
     DRAM Row Type:    Row 0: %[68:4]b%[68:0]b Row 3: %[68:7]b%[68:3]b
     00=SPM 01=EDO     Row 1: %[68:5]b%[68:1]b Row 4: %[67:4]b%[67:0]b
     10=SDRAM          Row 2: %[68:6]b%[68:2]b Row 5: %[67:5]b%[67:1]b
     11=Reserved       
     Memory Address Select Enable: %[67:2]d
%! Note: Intel don't document leadoff timing as the above in as many words,
%! but the answers are still the same :-)

 Programmable Attribute Map
      0F000-0FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R}\t0C000-0C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}
      0C400-0C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\t0C800-0CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}
      0CC00-0CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\t0D000-0D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}
      0D400-0D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\t0D800-0DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}
      0DC00-0DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\t0E000-0E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}
      0E400-0E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R}\t0E800-0EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R}
      0EC00-0EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R}

  Multi-Transaction Timer:           %[70:7-2]d
  System Management RAM Control:
     SMM Space Open:                 %[73:6]y
     SMM Space Closed:               %[73:5]y
     SMM Space Locked:               %[73:4]y
     Global SMRAM Enble:             %[73:3]y
     Compatible SMM Space base Seg:  %[73:2-0](C_BASE_SEG)
     High SMRAM Enable:              %[71:7]e
     Extended SMRAM Error:           %[71:6]y
     SMRAM Cache Strategy:           %[71:5]|WriteBack;WriteThru|
     SMRAM L1 Cache Enable:          %[71:4]e
     SMRAM L2 Cache Enable:          %[71:3]e
     TSEG Size:                      %[72:2-1](TSEG_SZ)
     TSEG Enable:                    %[72:0]y
!end

!enum SDMS
Normal SDRAM mode
NOP Command Enable
All Banks Precharge Command Enable
Mode Register Command Enable
CBR Cycle Enable
Reserved
Reserved
Reserved
Reserved
!end

!enum TSEG_SZ
(TOM-128k) to TOM
(TOM-256k) to TOM
(TOM-512k) to TOM
(TOM-1MB) to TOM
!end

!enum C_BASE_SEG
Reserved
Reserved
A0000-BFFFFh
Reserved
Reserved
Reserved
Reserved
Reserved
!end

%! end of file