80861237.pci

windwos环境下查看PCI驱动信息的源代码。

%! Detailed register description file for PCICFG.EXE by Ralf Brown
%!
%! Filename 80861237.PCI = Vendor 8086h, Device 1237h -- Intel 82441FX
%! Last Edit 9/27/97 by Ralf Brown
%!

[See file BLANK.PCI for description of formatting specification and how
to create your own device descriptions.]


!begin
82441FX System Controller registers in detail:
 PMC Control:     %[50]2x
 Cache Control:   cache size    %[52:7-6]|0K;256K;512K;reserved|
		  L2 RAM type	%[52:5-4](L2RAM)
		  Force L2 miss  %[52:1]y\tL1 cache %[52:0]Ed\tNA# %[52:3]Ed
 DRAM control:    DRAMs are %[57:4]|NOT;| self-refreshing
		  refresh   = %[57:2-0](Refresh)
		  DRAM hole = %[57:7-6]|none;512K-640K;15M-16M;reserved|
		  EDO Detect mode is %[57:3]ed
 Memory Top:      %[67<3]4dM
 DRAM Boundaries: %[60<3]4dM %[61<3]4dM %[62<3]4dM %[63<3]4dM %[64<3]4dM %[65<3]4dM %[66<3]4dM %[67<3]4dM
 DRAM Row Type:   %[55]2x
 DRAM timing:	  burst:  read = %[58:6-5](RBurst)   write = %[58:4-3](WBurst)
		  RAS-to-CAS   = %[58:2]|3;2| clocks
		  DRAM leadoff = %[58:1-0]|8/6/3;7/5/3;8/6/4;7/5/4| (read/write/precharge)
		  MA[11:2] buffer strength is %[58:7]|8;12|mA
 Multi-Trn Timer: %[70]d PCLKs
 CPU-Latency:     %[71]d
 SMRAM control:    SMM Space at segment %[72:2-0+8]1x000 is %[72:6]/open/ %[72:5]/closed/ %[72:4]/locked/
 Error Command:   %[90]2x
 Error Status:    %[91]2x
 Turbo Reset:     %[93]2x
 Programmable Attribute Map
	C000-C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}\tD000-D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}\tE000-E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}%
	F000-FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R}
	C400-C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\tD400-D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\tE400-E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R}
	C800-CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}\tD800-DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}\tE800-EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R}
	CC00-CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\tDC00-DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\tEC00-EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R}

 !% insert device description here

!end

!enum L2RAM
pipelined burst
async
reserved
two banks p.burst
!end

!enum Refresh
15.6 microseconds
32.2 microseconds
62.4 microseconds
125 microseconds
250 microseconds
reserved

!enum RBurst
x444/x444
x333/x444
x222/x333
x322/x333
!end

!enum WBurst
x444
x333
x222
reserved
!end

%! end of file