📄 decoder_latch.rpt
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Device-Specific Information: d:\laserinterface\cpld\decoder_latch.rpt
decoder_latch
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+--------------- LC115 q00
| +------------- LC117 q01
| | +----------- LC120 q02
| | | +--------- LC125 q03
| | | | +------- LC118 q10
| | | | | +----- LC128 q11
| | | | | | +--- LC126 q12
| | | | | | | +- LC123 q13
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'H'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC115-> * - - - - - - - | - - - - - - - * | <-- q00
LC117-> - * - - - - - - | - - - - - - - * | <-- q01
LC120-> - - * - - - - - | - - - - - - - * | <-- q02
LC125-> - - - * - - - - | - - - - - - - * | <-- q03
LC118-> - - - - * - - - | - - - - - - - * | <-- q10
LC128-> - - - - - * - - | - - - - - - - * | <-- q11
LC126-> - - - - - - * - | - - - - - - - * | <-- q12
LC123-> - - - - - - - * | - - - - - - - * | <-- q13
Pin
11 -> * * * * * * * * | - - - - - * * * | <-- a0
10 -> * * * * * * * * | - - - - - * * * | <-- a1
21 -> * - - - * - - - | - - - - - - - * | <-- d0
4 -> - * - - - * - - | - - - - - - - * | <-- d1
5 -> - - * - - - * - | - - - - - - - * | <-- d2
18 -> - - - * - - - * | - - - - - - - * | <-- d3
12 -> * * * * * * * * | - - - - - * * * | <-- wr
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\laserinterface\cpld\decoder_latch.rpt
decoder_latch
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
wr : INPUT;
-- Node name is 'q00' = '|74373:49|:12'
-- Equation name is 'q00', type is output
q00 = LCELL( _EQ001 $ GND);
_EQ001 = d0 & q00
# !a0 & !a1 & d0 & wr
# a0 & q00
# q00 & !wr
# a1 & q00;
-- Node name is 'q01' = '|74373:49|:13'
-- Equation name is 'q01', type is output
q01 = LCELL( _EQ002 $ GND);
_EQ002 = d1 & q01
# !a0 & !a1 & d1 & wr
# a0 & q01
# q01 & !wr
# a1 & q01;
-- Node name is 'q02' = '|74373:49|:14'
-- Equation name is 'q02', type is output
q02 = LCELL( _EQ003 $ GND);
_EQ003 = d2 & q02
# !a0 & !a1 & d2 & wr
# a0 & q02
# q02 & !wr
# a1 & q02;
-- Node name is 'q03' = '|74373:49|:15'
-- Equation name is 'q03', type is output
q03 = LCELL( _EQ004 $ GND);
_EQ004 = d3 & q03
# !a0 & !a1 & d3 & wr
# a0 & q03
# q03 & !wr
# a1 & q03;
-- Node name is 'q04' = '|74373:49|:16'
-- Equation name is 'q04', type is output
q04 = LCELL( _EQ005 $ GND);
_EQ005 = d4 & q04
# !a0 & !a1 & d4 & wr
# a0 & q04
# q04 & !wr
# a1 & q04;
-- Node name is 'q05' = '|74373:49|:17'
-- Equation name is 'q05', type is output
q05 = LCELL( _EQ006 $ GND);
_EQ006 = d5 & q05
# !a0 & !a1 & d5 & wr
# a0 & q05
# q05 & !wr
# a1 & q05;
-- Node name is 'q06' = '|74373:49|:18'
-- Equation name is 'q06', type is output
q06 = LCELL( _EQ007 $ GND);
_EQ007 = d6 & q06
# !a0 & !a1 & d6 & wr
# a0 & q06
# q06 & !wr
# a1 & q06;
-- Node name is 'q07' = '|74373:49|:19'
-- Equation name is 'q07', type is output
q07 = LCELL( _EQ008 $ GND);
_EQ008 = d7 & q07
# !a0 & !a1 & d7 & wr
# a0 & q07
# q07 & !wr
# a1 & q07;
-- Node name is 'q10' = '|74373:53|:12'
-- Equation name is 'q10', type is output
q10 = LCELL( _EQ009 $ GND);
_EQ009 = d0 & q10
# a0 & !a1 & d0 & wr
# !a0 & q10
# q10 & !wr
# a1 & q10;
-- Node name is 'q11' = '|74373:53|:13'
-- Equation name is 'q11', type is output
q11 = LCELL( _EQ010 $ GND);
_EQ010 = d1 & q11
# a0 & !a1 & d1 & wr
# !a0 & q11
# q11 & !wr
# a1 & q11;
-- Node name is 'q12' = '|74373:53|:14'
-- Equation name is 'q12', type is output
q12 = LCELL( _EQ011 $ GND);
_EQ011 = d2 & q12
# a0 & !a1 & d2 & wr
# !a0 & q12
# q12 & !wr
# a1 & q12;
-- Node name is 'q13' = '|74373:53|:15'
-- Equation name is 'q13', type is output
q13 = LCELL( _EQ012 $ GND);
_EQ012 = d3 & q13
# a0 & !a1 & d3 & wr
# !a0 & q13
# q13 & !wr
# a1 & q13;
-- Node name is 'q14' = '|74373:53|:16'
-- Equation name is 'q14', type is output
q14 = LCELL( _EQ013 $ GND);
_EQ013 = d4 & q14
# a0 & !a1 & d4 & wr
# !a0 & q14
# q14 & !wr
# a1 & q14;
-- Node name is 'q15' = '|74373:53|:17'
-- Equation name is 'q15', type is output
q15 = LCELL( _EQ014 $ GND);
_EQ014 = d5 & q15
# a0 & !a1 & d5 & wr
# !a0 & q15
# q15 & !wr
# a1 & q15;
-- Node name is 'q16' = '|74373:53|:18'
-- Equation name is 'q16', type is output
q16 = LCELL( _EQ015 $ GND);
_EQ015 = d6 & q16
# a0 & !a1 & d6 & wr
# !a0 & q16
# q16 & !wr
# a1 & q16;
-- Node name is 'q17' = '|74373:53|:19'
-- Equation name is 'q17', type is output
q17 = LCELL( _EQ016 $ GND);
_EQ016 = d7 & q17
# a0 & !a1 & d7 & wr
# !a0 & q17
# q17 & !wr
# a1 & q17;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\laserinterface\cpld\decoder_latch.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,854K
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