📄 8d.rpt
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8d
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 18 DFFE + 1 0 1 0 d0
- 3 - A 21 DFFE + 1 0 1 0 d1
- 5 - A 03 DFFE + 1 0 1 0 d2
- 8 - B 08 DFFE + 1 0 1 0 d3
- 8 - A 13 DFFE + 1 0 1 0 d4
- 5 - B 13 DFFE + 1 0 1 0 d5
- 2 - C 18 DFFE + 1 0 1 0 d6
- 1 - A 05 DFFE + 1 0 1 0 d7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus2\file\uart\8d.rpt
8d
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 2/ 48( 4%) 2/ 48( 4%) 1/16( 6%) 5/16( 31%) 0/16( 0%)
B: 1/ 96( 1%) 1/ 48( 2%) 1/ 48( 2%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 1/ 48( 2%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\file\uart\8d.rpt
8d
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: d:\maxplus2\file\uart\8d.rpt
8d
** EQUATIONS **
clk : INPUT;
in0 : INPUT;
in1 : INPUT;
in2 : INPUT;
in3 : INPUT;
in4 : INPUT;
in5 : INPUT;
in6 : INPUT;
in7 : INPUT;
-- Node name is 'd0' from file "8d.tdf" line 9, column 3
-- Equation name is 'd0', location is LC1_A18, type is buried.
d0 = DFFE( in0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'd1' from file "8d.tdf" line 9, column 3
-- Equation name is 'd1', location is LC3_A21, type is buried.
d1 = DFFE( in1, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'd2' from file "8d.tdf" line 9, column 3
-- Equation name is 'd2', location is LC5_A3, type is buried.
d2 = DFFE( in2, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'd3' from file "8d.tdf" line 9, column 3
-- Equation name is 'd3', location is LC8_B8, type is buried.
d3 = DFFE( in3, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'd4' from file "8d.tdf" line 9, column 3
-- Equation name is 'd4', location is LC8_A13, type is buried.
d4 = DFFE( in4, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'd5' from file "8d.tdf" line 9, column 3
-- Equation name is 'd5', location is LC5_B13, type is buried.
d5 = DFFE( in5, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'd6' from file "8d.tdf" line 9, column 3
-- Equation name is 'd6', location is LC2_C18, type is buried.
d6 = DFFE( in6, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'd7' from file "8d.tdf" line 9, column 3
-- Equation name is 'd7', location is LC1_A5, type is buried.
d7 = DFFE( in7, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'out0' from file "8d.tdf" line 16, column 5
-- Equation name is 'out0', type is output
out0 = d0;
-- Node name is 'out1' from file "8d.tdf" line 16, column 5
-- Equation name is 'out1', type is output
out1 = d1;
-- Node name is 'out2' from file "8d.tdf" line 16, column 5
-- Equation name is 'out2', type is output
out2 = d2;
-- Node name is 'out3' from file "8d.tdf" line 16, column 5
-- Equation name is 'out3', type is output
out3 = d3;
-- Node name is 'out4' from file "8d.tdf" line 16, column 5
-- Equation name is 'out4', type is output
out4 = d4;
-- Node name is 'out5' from file "8d.tdf" line 16, column 5
-- Equation name is 'out5', type is output
out5 = d5;
-- Node name is 'out6' from file "8d.tdf" line 16, column 5
-- Equation name is 'out6', type is output
out6 = d6;
-- Node name is 'out7' from file "8d.tdf" line 16, column 5
-- Equation name is 'out7', type is output
out7 = d7;
Project Information d:\maxplus2\file\uart\8d.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,836K
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