📄 m1024.rpt
字号:
- 5 - B 08 AND2 0 4 0 3 :65
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus2\file\uart\m1024.rpt
m1024
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\file\uart\m1024.rpt
m1024
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 in
Device-Specific Information: d:\maxplus2\file\uart\m1024.rpt
m1024
** EQUATIONS **
in : INPUT;
-- Node name is 'fp0' from file "m1024.tdf" line 8, column 4
-- Equation name is 'fp0', location is LC3_B5, type is buried.
fp0 = DFFE(!fp0, GLOBAL( in), VCC, VCC, VCC);
-- Node name is 'fp1' from file "m1024.tdf" line 8, column 4
-- Equation name is 'fp1', location is LC2_B5, type is buried.
fp1 = DFFE( _EQ001, GLOBAL( in), VCC, VCC, VCC);
_EQ001 = fp0 & !fp1
# !fp0 & fp1;
-- Node name is 'fp2' from file "m1024.tdf" line 8, column 4
-- Equation name is 'fp2', location is LC4_B5, type is buried.
fp2 = DFFE( _EQ002, GLOBAL( in), VCC, VCC, VCC);
_EQ002 = !fp0 & fp2
# !fp1 & fp2
# fp0 & fp1 & !fp2;
-- Node name is 'fp3' from file "m1024.tdf" line 8, column 4
-- Equation name is 'fp3', location is LC5_B5, type is buried.
fp3 = DFFE( _EQ003, GLOBAL( in), VCC, VCC, VCC);
_EQ003 = !fp0 & fp3
# !fp1 & fp3
# !fp2 & fp3
# fp0 & fp1 & fp2 & !fp3;
-- Node name is 'fp4' from file "m1024.tdf" line 8, column 4
-- Equation name is 'fp4', location is LC2_B8, type is buried.
fp4 = DFFE( _EQ004, GLOBAL( in), VCC, VCC, VCC);
_EQ004 = fp4 & !_LC1_B5
# !fp4 & _LC1_B5;
-- Node name is 'fp5' from file "m1024.tdf" line 8, column 4
-- Equation name is 'fp5', location is LC3_B8, type is buried.
fp5 = DFFE( _EQ005, GLOBAL( in), VCC, VCC, VCC);
_EQ005 = !fp4 & fp5
# fp5 & !_LC1_B5
# fp4 & !fp5 & _LC1_B5;
-- Node name is 'fp6' from file "m1024.tdf" line 8, column 4
-- Equation name is 'fp6', location is LC4_B8, type is buried.
fp6 = DFFE( _EQ006, GLOBAL( in), VCC, VCC, VCC);
_EQ006 = !fp4 & fp6
# fp6 & !_LC1_B5
# !fp5 & fp6
# fp4 & fp5 & !fp6 & _LC1_B5;
-- Node name is 'fp7' from file "m1024.tdf" line 8, column 4
-- Equation name is 'fp7', location is LC6_B8, type is buried.
fp7 = DFFE( _EQ007, GLOBAL( in), VCC, VCC, VCC);
_EQ007 = fp7 & !_LC5_B8
# !fp7 & _LC5_B8;
-- Node name is 'fp8' from file "m1024.tdf" line 8, column 4
-- Equation name is 'fp8', location is LC7_B8, type is buried.
fp8 = DFFE( _EQ008, GLOBAL( in), VCC, VCC, VCC);
_EQ008 = !fp7 & fp8
# fp8 & !_LC5_B8
# fp7 & !fp8 & _LC5_B8;
-- Node name is 'fp9' from file "m1024.tdf" line 8, column 4
-- Equation name is 'fp9', location is LC1_B8, type is buried.
fp9 = DFFE( _EQ009, GLOBAL( in), VCC, VCC, VCC);
_EQ009 = !fp7 & fp9
# fp9 & !_LC5_B8
# !fp8 & fp9
# fp7 & fp8 & !fp9 & _LC5_B8;
-- Node name is '9hz' from file "m1024.tdf" line 11, column 2
-- Equation name is '9hz', type is output
9hz = fp9;
-- Node name is ':53' from file "m1024.tdf" line 13, column 13
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = LCELL( _EQ010);
_EQ010 = fp0 & fp1 & fp2 & fp3;
-- Node name is ':65' from file "m1024.tdf" line 13, column 13
-- Equation name is '_LC5_B8', type is buried
_LC5_B8 = LCELL( _EQ011);
_EQ011 = fp4 & fp5 & fp6 & _LC1_B5;
Project Information d:\maxplus2\file\uart\m1024.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,415K
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