📄 urat.rpt
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Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\maxplus2\file\uart\urat.rpt
urat
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
59 - - C -- OUTPUT 0 1 0 0 fs_clk
62 - - C -- OUTPUT 0 1 0 0 fs_dao
66 - - B -- OUTPUT 0 1 0 0 fs_ld
25 - - B -- OUTPUT 0 1 0 0 Fs_po0
58 - - C -- OUTPUT 0 1 0 0 Fs_po1
38 - - - 10 OUTPUT 0 1 0 0 Fs_po2
29 - - C -- OUTPUT 0 1 0 0 Fs_po3
61 - - C -- OUTPUT 0 1 0 0 Fs_po4
27 - - C -- OUTPUT 0 1 0 0 Fs_po5
60 - - C -- OUTPUT 0 1 0 0 Fs_po6
28 - - C -- OUTPUT 0 1 0 0 Fs_po7
81 - - - 22 OUTPUT 0 1 0 0 Fs_po8
54 - - - 21 OUTPUT 0 1 0 0 Fs_po9
37 - - - 09 OUTPUT 0 1 0 0 Fs_Txd
65 - - B -- OUTPUT 0 1 0 0 fs_1p
7 - - - 03 OUTPUT 0 1 0 0 js_clk
6 - - - 04 OUTPUT 0 1 0 0 Js_dao
24 - - B -- OUTPUT 0 1 0 0 js_po0
23 - - B -- OUTPUT 0 1 0 0 js_po1
22 - - B -- OUTPUT 0 1 0 0 js_po2
21 - - B -- OUTPUT 0 1 0 0 js_po3
19 - - A -- OUTPUT 0 1 0 0 js_po4
18 - - A -- OUTPUT 0 1 0 0 js_po5
17 - - A -- OUTPUT 0 1 0 0 js_po6
16 - - A -- OUTPUT 0 1 0 0 js_po7
70 - - A -- OUTPUT 0 1 0 0 1p
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\maxplus2\file\uart\urat.rpt
urat
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - C 17 LCELL s 1 0 1 0 fs_clk~1
- 2 - C 18 DFFE + 0 2 0 4 |fs_cnt:113|cnt0
- 1 - C 18 DFFE + 0 3 0 4 |fs_cnt:113|cnt1
- 4 - C 18 DFFE + 0 4 0 3 |fs_cnt:113|cnt2
- 6 - C 18 DFFE + 0 4 0 2 |fs_cnt:113|cnt3
- 7 - C 18 DFFE + 0 1 0 2 |fs_cnt:113|cnt4
- 5 - C 18 OR2 ! 0 4 0 4 |fs_cnt:113|:50
- 3 - C 16 AND2 0 2 0 1 |fs_cnt:113|:57
- 3 - C 18 OR2 s 0 3 0 1 |fs_cnt:113|~95~1
- 1 - C 16 OR2 0 3 1 1 |fs_cnt:113|:95
- 4 - C 16 OR2 ! 1 1 0 11 |fs_sft:115|ld
- 2 - C 09 DFFE +s ! 0 2 1 0 |fs_sft:115|sft_reg0~1
- 8 - C 09 DFFE + ! 0 2 1 0 |fs_sft:115|sft_reg0
- 7 - C 09 DFFE + 0 2 1 2 |fs_sft:115|sft_reg1
- 6 - C 09 DFFE + 1 2 1 1 |fs_sft:115|sft_reg2
- 5 - C 09 DFFE + 1 2 1 1 |fs_sft:115|sft_reg3
- 3 - C 09 DFFE + 1 2 1 1 |fs_sft:115|sft_reg4
- 1 - C 09 DFFE + 1 2 1 1 |fs_sft:115|sft_reg5
- 4 - C 09 DFFE + 1 2 1 1 |fs_sft:115|sft_reg6
- 2 - C 22 DFFE + 1 2 1 1 |fs_sft:115|sft_reg7
- 3 - C 22 DFFE + 1 2 1 1 |fs_sft:115|sft_reg8
- 1 - C 22 DFFE + 1 1 1 1 |fs_sft:115|sft_reg9
- 6 - A 08 DFFE 0 2 0 2 |g1p:77|:1
- 7 - A 08 DFFE 0 3 0 1 |g1p:77|:2
- 8 - A 08 OR2 ! 0 2 1 8 |g1p:77|1p (|g1p:77|:3)
- 5 - C 16 DFFE + 0 0 0 2 |g1p:116|:1
- 6 - C 16 DFFE + 0 1 0 1 |g1p:116|:2
- 8 - C 16 OR2 ! 0 2 1 1 |g1p:116|1p (|g1p:116|:3)
- 6 - B 07 DFFE 0 2 1 0 |js_sft:95|js_buf0
- 4 - B 07 DFFE 0 2 1 0 |js_sft:95|js_buf1
- 2 - B 07 DFFE 0 2 1 0 |js_sft:95|js_buf2
- 1 - B 07 DFFE 0 2 1 0 |js_sft:95|js_buf3
- 7 - A 02 DFFE 0 2 1 0 |js_sft:95|js_buf4
- 5 - A 11 DFFE 0 2 1 0 |js_sft:95|js_buf5
- 3 - A 11 DFFE 0 2 1 0 |js_sft:95|js_buf6
- 1 - A 11 DFFE 0 2 1 0 |js_sft:95|js_buf7
- 8 - B 07 DFFE 0 2 0 1 |js_sft:95|sft_reg1
- 7 - B 07 DFFE 0 2 0 2 |js_sft:95|sft_reg2
- 5 - B 07 DFFE 0 2 0 2 |js_sft:95|sft_reg3
- 3 - B 07 DFFE 0 2 0 2 |js_sft:95|sft_reg4
- 2 - A 11 DFFE 0 2 0 2 |js_sft:95|sft_reg5
- 8 - A 11 DFFE 0 2 0 2 |js_sft:95|sft_reg6
- 7 - A 11 DFFE 0 2 0 2 |js_sft:95|sft_reg7
- 6 - A 11 DFFE 0 2 0 2 |js_sft:95|sft_reg8
- 4 - A 11 DFFE 1 1 0 1 |js_sft:95|sft_reg9
- 3 - A 08 DFFE 0 3 0 3 |js_tb:93|jsck0
- 2 - A 08 DFFE 0 4 0 2 |js_tb:93|jsck1
- 4 - A 08 DFFE 0 5 0 1 |js_tb:93|jsck2
- 8 - A 03 DFFE 0 4 1 11 |js_tb:93|jsck3
- 6 - A 03 DFFE 0 5 0 2 |js_tb:93|jsck4
- 5 - A 03 DFFE 0 5 0 4 |js_tb:93|jsck5
- 7 - A 03 DFFE 0 5 0 3 |js_tb:93|jsck6
- 4 - A 03 DFFE 0 5 0 4 |js_tb:93|jsck7
- 2 - A 03 OR2 ! 0 3 0 6 |js_tb:93|:54
- 1 - A 08 AND2 0 3 0 3 |js_tb:93|:65
- 3 - A 03 AND2 0 3 0 3 |js_tb:93|:73
- 1 - A 03 AND2 ! 0 4 1 9 |js_tb:93|:122
- 8 - C 04 DFFE 1 3 0 3 |s_clk:40|fp0
- 6 - C 04 DFFE 1 2 0 2 |s_clk:40|fp1
- 4 - C 04 DFFE 1 2 0 2 |s_clk:40|fp2
- 4 - C 07 DFFE 1 2 0 4 |s_clk:40|fp3
- 5 - C 07 DFFE 1 3 0 3 |s_clk:40|fp4
- 7 - C 07 DFFE 1 3 0 2 |s_clk:40|fp5
- 2 - C 07 DFFE 1 2 0 2 |s_clk:40|fp6
- 7 - C 04 DFFE 1 3 0 3 |s_clk:40|fp7
- 1 - C 04 AND2 ! 0 4 0 10 |s_clk:40|:44
- 5 - C 04 AND2 0 2 0 4 |s_clk:40|:47
- 3 - C 07 AND2 s 0 3 0 1 |s_clk:40|~53~1
- 1 - C 07 AND2 s 0 3 0 3 |s_clk:40|~53~2
- 2 - C 04 OR2 ! 0 3 0 7 |s_clk:40|:55
- 3 - C 04 AND2 0 2 0 4 |s_clk:40|:66
- 6 - C 07 AND2 0 2 0 1 |s_clk:40|:70
- 8 - C 07 AND2 0 4 0 2 |s_clk:40|:78
- 5 - A 08 AND2 1 1 0 2 :29
- 2 - C 16 OR2 ! 0 2 1 6 :117
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus2\file\uart\urat.rpt
urat
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 1/ 96( 1%) 7/ 48( 14%) 2/ 48( 4%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 11/ 96( 11%) 10/ 48( 20%) 10/ 48( 20%) 1/16( 6%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\file\uart\urat.rpt
urat
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 fs_clock
DFF 13 |js_tb:93|jsck3
LCELL 10 |js_tb:93|:122
LCELL 10 |s_clk:40|:44
INPUT 8 20Mhz
Device-Specific Information: d:\maxplus2\file\uart\urat.rpt
urat
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 11 |fs_sft:115|ld
LCELL 9 |g1p:77|1p
LCELL 7 :117
INPUT 2 Fs_load
LCELL 2 :29
Device-Specific Information: d:\maxplus2\file\uart\urat.rpt
urat
** EQUATIONS **
fs_clock : INPUT;
Fs_load : INPUT;
Fs_pi0 : INPUT;
Fs_pi1 : INPUT;
Fs_pi2 : INPUT;
Fs_pi3 : INPUT;
Fs_pi4 : INPUT;
Fs_pi5 : INPUT;
Fs_pi6 : INPUT;
Fs_pi7 : INPUT;
Js_Rxd : INPUT;
20Mhz : INPUT;
-- Node name is 'fs_clk'
-- Equation name is 'fs_clk', type is output
fs_clk = _LC5_C17;
-- Node name is 'fs_clk~1'
-- Equation name is 'fs_clk~1', location is LC5_C17, type is buried.
-- synthesized logic cell
_LC5_C17 = LCELL( fs_clock);
-- Node name is 'fs_dao'
-- Equation name is 'fs_dao', type is output
fs_dao = !_LC1_C16;
-- Node name is 'fs_ld'
-- Equation name is 'fs_ld', type is output
fs_ld = _LC2_C16;
-- Node name is 'Fs_po0'
-- Equation name is 'Fs_po0', type is output
Fs_po0 = _LC8_C9;
-- Node name is 'Fs_po1'
-- Equation name is 'Fs_po1', type is output
Fs_po1 = _LC7_C9;
-- Node name is 'Fs_po2'
-- Equation name is 'Fs_po2', type is output
Fs_po2 = _LC6_C9;
-- Node name is 'Fs_po3'
-- Equation name is 'Fs_po3', type is output
Fs_po3 = _LC5_C9;
-- Node name is 'Fs_po4'
-- Equation name is 'Fs_po4', type is output
Fs_po4 = _LC3_C9;
-- Node name is 'Fs_po5'
-- Equation name is 'Fs_po5', type is output
Fs_po5 = _LC1_C9;
-- Node name is 'Fs_po6'
-- Equation name is 'Fs_po6', type is output
Fs_po6 = _LC4_C9;
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