📄 test.rpt
字号:
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus2\file\uart\test.rpt
test
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 0/ 48( 0%) 3/ 48( 6%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 3/ 48( 6%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\file\uart\test.rpt
test
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 clk
Device-Specific Information: d:\maxplus2\file\uart\test.rpt
test
** EQUATIONS **
clk : INPUT;
load : INPUT;
pi0 : INPUT;
pi1 : INPUT;
pi2 : INPUT;
pi3 : INPUT;
pi4 : INPUT;
pi5 : INPUT;
pi6 : INPUT;
pi7 : INPUT;
-- Node name is 'po0'
-- Equation name is 'po0', type is output
po0 = _LC1_B13;
-- Node name is 'po1'
-- Equation name is 'po1', type is output
po1 = _LC3_B13;
-- Node name is 'po2'
-- Equation name is 'po2', type is output
po2 = _LC7_A14;
-- Node name is 'po3'
-- Equation name is 'po3', type is output
po3 = _LC6_A14;
-- Node name is 'po4'
-- Equation name is 'po4', type is output
po4 = _LC8_A14;
-- Node name is 'po5'
-- Equation name is 'po5', type is output
po5 = _LC4_A14;
-- Node name is 'po6'
-- Equation name is 'po6', type is output
po6 = _LC2_A14;
-- Node name is 'po7'
-- Equation name is 'po7', type is output
po7 = _LC1_A14;
-- Node name is 'po8'
-- Equation name is 'po8', type is output
po8 = _LC3_A14;
-- Node name is 'po9'
-- Equation name is 'po9', type is output
po9 = _LC5_A14;
-- Node name is 'so'
-- Equation name is 'so', type is output
so = _LC5_B13;
-- Node name is '|fs_sft:1|sft_reg0~1' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC5_B13', type is buried
-- synthesized logic cell
_LC5_B13 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC3_B13
# load;
-- Node name is '|fs_sft:1|sft_reg0' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC3_B13
# load;
-- Node name is '|fs_sft:1|sft_reg1' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC7_A14 & !load;
-- Node name is '|fs_sft:1|sft_reg2' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC7_A14', type is buried
_LC7_A14 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC6_A14 & !load
# load & pi0;
-- Node name is '|fs_sft:1|sft_reg3' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC6_A14', type is buried
_LC6_A14 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC8_A14 & !load
# load & pi1;
-- Node name is '|fs_sft:1|sft_reg4' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC8_A14', type is buried
_LC8_A14 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC4_A14 & !load
# load & pi2;
-- Node name is '|fs_sft:1|sft_reg5' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC4_A14', type is buried
_LC4_A14 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC2_A14 & !load
# load & pi3;
-- Node name is '|fs_sft:1|sft_reg6' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC1_A14 & !load
# load & pi4;
-- Node name is '|fs_sft:1|sft_reg7' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC3_A14 & !load
# load & pi5;
-- Node name is '|fs_sft:1|sft_reg8' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC3_A14', type is buried
_LC3_A14 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = _LC5_A14 & !load
# load & pi6;
-- Node name is '|fs_sft:1|sft_reg9' from file "fs_sft.tdf" line 10, column 9
-- Equation name is '_LC5_A14', type is buried
_LC5_A14 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = pi7
# !load;
Project Information d:\maxplus2\file\uart\test.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,833K
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