dpram2.gfl

这是我用vhdl语言

# XST (Creating Lso File) : 
dpram2.lso
# xst flow : RunXST
dpram2.syr
dpram2.prj
dpram2.sprj
dpram2.ana
dpram2.stx
dpram2.cmd_log
dpram2.ngc
dpram2.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\xilinx\bin\dpram2/_ngo
dpram2.ngd
dpram2_ngdbuild.nav
dpram2.bld
.untf
dpram2.cmd_log
# Implementation : Map
dpram2_map.ncd
dpram2.ngm
dpram2.pcf
dpram2.nc1
dpram2.mrp
dpram2_map.mrp
dpram2.mdf
__projnav/map.log
dpram2.cmd_log
MAP_NO_GUIDE_FILE_CPF "dpram2"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
dpram2.twr
dpram2.twx
dpram2.tsi
dpram2.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
dpram2.ncd
dpram2.par
dpram2.pad
dpram2_pad.txt
dpram2_pad.csv
dpram2.pad_txt
dpram2.dly
reportgen.log
dpram2.xpi
dpram2.grf
dpram2.itr
dpram2_last_par.ncd
__projnav/par.log
dpram2.placed_ncd_tracker
dpram2.routed_ncd_tracker
dpram2.cmd_log
PAR_NO_GUIDE_FILE_CPF "dpram2"
# Generate Programming File
__projnav/dpram2_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
dpram2.ut
# Generate Programming File
dpram2.bgn
dpram2.rbt
dpram2.ll
dpram2.msk
dpram2.drc
dpram2.nky
dpram2.bit
dpram2.bin
dpram2.isc
dpram2.cmd_log
# ProjNav -> New Source -> TBW
c:\xilinx\bin\dpram2\__projnav\hb_cmds
# ProjNav -> New Source -> TBW
c:\xilinx\bin\dpram2\__projnav\hb_cmds
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
test.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
test.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
test.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
test.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher Waveform : PDCL (jhdparse)