dpram2.syr

这是我用vhdl语言

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
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--> Reading design: dpram2.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : dpram2.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : dpram2
Output Format                      : NGC
Target Device                      : xc2s300e-6-pq208

---- Source Options
Top Module Name                    : dpram2
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : dpram2.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file c:/xilinx/bin/dpram2/dpram2.vhd in Library work.
Entity <dpram2> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <dpram2> (Architecture <behavioral>).
Entity <dpram2> analyzed. Unit <dpram2> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <dpram2>.
    Related source file is c:/xilinx/bin/dpram2/dpram2.vhd.
    Using one-hot encoding for signal <$n0017>.
    Found 8-bit register for signal <data1_out>.
    Found 8-bit register for signal <data2_out>.
    Found 8-bit 32-to-1 multiplexer for signal <$n0036> created at line 179.
    Found 8-bit 32-to-1 multiplexer for signal <$n0037> created at line 188.
    Found 8-bit 32-to-1 multiplexer for signal <$n0038> created at line 193.
    Found 8-bit 32-to-1 multiplexer for signal <$n0039> created at line 202.
    Found 5-bit adder for signal <$n0353> created at line 184.
    Found 5-bit adder for signal <$n0354> created at line 198.
    Found 5-bit comparator equal for signal <$n0355> created at line 284.
    Found 5-bit comparator equal for signal <$n0356> created at line 301.
    Found 5-bit comparator equal for signal <$n0357> created at line 318.
    Found 5-bit comparator equal for signal <$n0358> created at line 339.
    Found 5-bit register for signal <addr1_i>.
    Found 5-bit register for signal <addr2_i>.
    Found 256-bit register for signal <ram>.
    Found 1-bit register for signal <rd1_ack>.
    Found 1-bit register for signal <rd2_ack>.
    Found 25-bit register for signal <state>.
    Found 1-bit register for signal <wr1_ack>.
    Found 1-bit register for signal <wr2_ack>.
    Found 1024 1-bit 2-to-1 multiplexers.
INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred for signal <ram>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
    Summary:
	inferred 311 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   4 Comparator(s).
	inferred 1056 Multiplexer(s).
Unit <dpram2> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 41
  25-bit register                  : 1
  1-bit register                   : 4
  5-bit register                   : 2
  8-bit register                   : 34
# Multiplexers                     : 132
  2-to-1 multiplexer               : 128
  8-bit 32-to-1 multiplexer        : 4
# Adders/Subtractors               : 2
  5-bit adder                      : 2
# Comparators                      : 4
  5-bit comparator equal           : 4

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <dpram2> ...
Loading device for application Xst from file '2s300e.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dpram2, actual ratio is 59.
FlipFlop addr2_i_0 has been replicated 8 time(s)
FlipFlop addr1_i_0 has been replicated 8 time(s)
FlipFlop addr2_i_0 has been replicated 1 time(s)
FlipFlop addr1_i_0 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : dpram2.ngr
Top Level Output File Name         : dpram2
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 49

Macro Statistics :
# Registers                        : 41
#      1-bit register              : 4
#      25-bit register             : 1
#      5-bit register              : 2
#      8-bit register              : 34
# Multiplexers                     : 132
#      2-to-1 multiplexer          : 128
#      8-bit 32-to-1 multiplexer   : 4
# Adders/Subtractors               : 2
#      5-bit adder                 : 2
# Comparators                      : 4
#      5-bit comparator equal      : 4

Cell Usage :
# BELS                             : 3989
#      BUF                         : 2
#      GND                         : 1
#      LUT1                        : 2
#      LUT1_L                      : 8
#      LUT2                        : 54
#      LUT2_D                      : 6
#      LUT2_L                      : 126
#      LUT3                        : 960
#      LUT3_D                      : 71
#      LUT3_L                      : 34
#      LUT4                        : 1603
#      LUT4_D                      : 104
#      LUT4_L                      : 573
#      MUXCY                       : 20
#      MUXF5                       : 288
#      MUXF6                       : 128
#      VCC                         : 1
#      XORCY                       : 8
# FlipFlops/Latches                : 329
#      FDE                         : 25
#      FDS                         : 276
#      FDSE                        : 28
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 48
#      IBUF                        : 32
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300epq208-6 

 Number of Slices:                    1898  out of   3072    61%  
 Number of Slice Flip Flops:           329  out of   6144     5%  
 Number of 4 input LUTs:              3541  out of   6144    57%  
 Number of bonded IOBs:                 48  out of    146    32%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 329   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 19.500ns (Maximum Frequency: 51.282MHz)
   Minimum input arrival time before clock: 24.098ns
   Maximum output required time after clock: 6.744ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               19.500ns (Levels of Logic = 8)
  Source:            wr2_ack (FF)
  Destination:       ram_22_6 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: wr2_ack to ram_22_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              1   0.992   0.920  wr2_ack (wr2_ack)
     LUT4_D:I0->LO         1   0.468   0.100  _n00051 (N157728)
     LUT4:I0->O            8   0.468   2.050  _n00111 (_n0011)
     LUT4_D:I0->O         12   0.468   2.450  _n00151 (_n0015)
     LUT4_D:I3->O         17   0.468   2.850  _n0017<21>_SW113 (_n0017<21>)
     LUT3_D:I2->O          1   0.468   0.920  _n048625 (CHOICE266)
     LUT4:I3->O           16   0.468   2.800  _n048641_1 (_n048641_1)
     LUT4_D:I1->O          7   0.468   1.950  Ker9831852 (N98320)
     LUT2_L:I0->LO         1   0.468   0.000  _n0076<5>1111 (N153180)
     FDS:D                     0.724          ram_26_5
    ----------------------------------------
    Total                     19.500ns (5.460ns logic, 14.040ns route)
                                       (28.0% logic, 72.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              24.098ns (Levels of Logic = 10)
  Source:            wr2 (PAD)
  Destination:       ram_22_6 (FF)
  Destination Clock: clk rising

  Data Path: wr2 to ram_22_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            14   0.797   2.650  wr2_IBUF (wr2_IBUF)
     LUT3:I2->O            2   0.468   1.150  Ker966351 (N96637)
     LUT4:I3->O           35   0.468   3.375  Ker965691 (N96571)
     LUT2:I0->O            6   0.468   1.850  _n0017<20>_SW10 (CHOICE10)
     LUT4_D:I0->O         15   0.468   2.750  _n0017<20>_SW16 (_n0017<20>)
     LUT4:I3->O            1   0.468   0.920  _n048622 (CHOICE264)
     LUT3_D:I0->O          1   0.468   0.920  _n048625 (CHOICE266)
     LUT4:I3->O           16   0.468   2.800  _n048641_1 (_n048641_1)
     LUT4_D:I1->O          7   0.468   1.950  Ker9831852 (N98320)
     LUT2_L:I0->LO         1   0.468   0.000  _n0076<5>1111 (N153180)
     FDS:D                     0.724          ram_26_5
    ----------------------------------------
    Total                     24.098ns (5.733ns logic, 18.365ns route)
                                       (23.8% logic, 76.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              6.744ns (Levels of Logic = 1)
  Source:            data1_out_7 (FF)
  Destination:       data1_out<7> (PAD)
  Source Clock:      clk rising

  Data Path: data1_out_7 to data1_out<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              2   0.992   1.150  data1_out_7 (data1_out_7)
     OBUF:I->O                 4.602          data1_out_7_OBUF (data1_out<7>)
    ----------------------------------------
    Total                      6.744ns (5.594ns logic, 1.150ns route)
                                       (82.9% logic, 17.1% route)

=========================================================================
CPU : 93.81 / 94.26 s | Elapsed : 94.00 / 94.00 s
 
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Total memory usage is 163684 kilobytes