traplog.tlg

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· TLG 代码 · 共 11 行

Synthesizing work.top.gen
Synthesizing work.cmp_eq.cell_level
Synthesizing work.eq_element_onebit.eqn
Synthesizing virtex.muxcy_l.syn_black_box
Post processing for virtex.muxcy_l.syn_black_box
Post processing for work.eq_element_onebit.eqn
Synthesizing work.eq_element.eqn
Post processing for work.eq_element.eqn
Post processing for work.cmp_eq.cell_level
Post processing for work.top.gen