virtex2.vhd

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· VHDL 代码 · 共 2,783 行 · 第 1/5 页

VHD
2,783 行
字号
12345
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_4 : component is true;
component IOBUF_LVCMOS15_S_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_6 : component is true;
component IOBUF_LVCMOS15_S_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_8 : component is true;
component IOBUF_LVCMOS18
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18 : component is true;
component IOBUF_LVCMOS18_F_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_12 : component is true;
component IOBUF_LVCMOS18_F_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_16 : component is true;
component IOBUF_LVCMOS18_F_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_2 : component is true;
component IOBUF_LVCMOS18_F_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_4 : component is true;
component IOBUF_LVCMOS18_F_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_6 : component is true;
component IOBUF_LVCMOS18_F_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_8 : component is true;
component IOBUF_LVCMOS18_S_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_12 : component is true;
component IOBUF_LVCMOS18_S_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_16 : component is true;
component IOBUF_LVCMOS18_S_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_2 : component is true;
component IOBUF_LVCMOS18_S_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_4 : component is true;
component IOBUF_LVCMOS18_S_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_6 : component is true;
component IOBUF_LVCMOS18_S_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_8 : component is true;
component IOBUF_LVCMOS2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS2 : component is true;
component IOBUF_LVCMOS25
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25 : component is true;
component IOBUF_LVCMOS25_F_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_12 : component is true;
component IOBUF_LVCMOS25_F_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_16 : component is true;
component IOBUF_LVCMOS25_F_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_2 : component is true;
component IOBUF_LVCMOS25_F_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_24 : component is true;
component IOBUF_LVCMOS25_F_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_4 : component is true;
component IOBUF_LVCMOS25_F_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_6 : component is true;
component IOBUF_LVCMOS25_F_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_8 : component is true;
component IOBUF_LVCMOS25_S_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_12 : component is true;
component IOBUF_LVCMOS25_S_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_16 : component is true;
component IOBUF_LVCMOS25_S_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_2 : component is true;
component IOBUF_LVCMOS25_S_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_24 : component is true;
component IOBUF_LVCMOS25_S_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_4 : component is true;
component IOBUF_LVCMOS25_S_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_6 : component is true;
component IOBUF_LVCMOS25_S_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_8 : component is true;
component IOBUF_LVCMOS33
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33 : component is true;
component IOBUF_LVCMOS33_F_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_F_12 : component is true;
component IOBUF_LVCMOS33_F_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_F_16 : component is true;
component IOBUF_LVCMOS33_F_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_F_2 : component is true;
component IOBUF_LVCMOS33_F_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_F_24 : component is true;
component IOBUF_LVCMOS33_F_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_F_4 : component is true;
component IOBUF_LVCMOS33_F_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_F_6 : component is true;
component IOBUF_LVCMOS33_F_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_F_8 : component is true;
component IOBUF_LVCMOS33_S_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_S_12 : component is true;
component IOBUF_LVCMOS33_S_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_S_16 : component is true;
component IOBUF_LVCMOS33_S_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_S_2 : component is true;
component IOBUF_LVCMOS33_S_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_S_24 : component is true;
component IOBUF_LVCMOS33_S_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_S_4 : component is true;
component IOBUF_LVCMOS33_S_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_S_6 : component is true;
component IOBUF_LVCMOS33_S_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVCMOS33_S_8 : component is true;
component IOBUF_LVDCI_15
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_15 : component is true;
component IOBUF_LVDCI_18
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_18 : component is true;
component IOBUF_LVDCI_25
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_25 : component is true;
component IOBUF_LVDCI_33
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_33 : component is true;
component IOBUF_LVDCI_DV2_15
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_15 : component is true;
component IOBUF_LVDCI_DV2_18
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_18 : component is true;
component IOBUF_LVDCI_DV2_25
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_25 : component is true;
component IOBUF_LVDCI_DV2_33
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_33 : component is true;
component IOBUF_LVTTL
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL : component is true;
component IOBUF_LVTTL_F_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_12 : component is true;
component IOBUF_LVTTL_F_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_16 : component is true;
component IOBUF_LVTTL_F_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_2 : component is true;
component IOBUF_LVTTL_F_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_24 : component is true;
component IOBUF_LVTTL_F_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_4 : component is true;
component IOBUF_LVTTL_F_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_6 : component is true;
component IOBUF_LVTTL_F_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
12345

virtex2.vhd - 源码说明

本页面展示了「FPGA-CPLD_DesignTool(8-9-10)源代码」中的 virtex2.vhd 源码文件，采用 VHDL 编程语言编写，共 2,783 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

虫虫下载站收录了大量与FPGA-CPLD_DesignTool相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?