top.v

FPGA-CPLD_DesignTool(8-9-10)源代码

// Xilinx Verilog produced by program ngd2ver F.28
// Command: top.nga 
// Input file: top.nga
// Output file: top.v
// Design name: top
// Xilinx: J:/eda/Xilinx
// # of Entities: 1
// Device: 2v40cs144-5 (PRODUCTION 1.114 2002-12-13, STEPPING 1)

// The output of ngd2ver is a simulation model. This netlist uses simulation
// primitives which may not represent the true implementation of the device,
// however the netlist is functionally correct and should not be modified.
// This file cannot be synthesized and should only be used with supported
// simulation, static timing analysis and formal verification software tools.
// Please refer to the documentation on using third party static timing analysis
// and formal verification software to use the netlist for that purpose.

`timescale 1 ns/1 ps

module top (
  modc_out, modb_clk_pad, mod_c_out, obuft_out, modb_out, modc_data, moda_clk_pad, ipad_dll_clk_in, modb_data, modc_clk_pad, moda_data, top2a_c, top2b
, dll_rst, moda_out
);
  output modc_out;
  input modb_clk_pad;
  output mod_c_out;
  output obuft_out;
  output modb_out;
  input modc_data;
  input moda_clk_pad;
  input ipad_dll_clk_in;
  input modb_data;
  input modc_clk_pad;
  input moda_data;
  input top2a_c;
  input top2b;
  input dll_rst;
  output moda_out;
  wire moda_clk;
  wire \instance_a/Q3_OUT ;
  wire \instance_a/Q0_OUT ;
  wire \instance_a/Q1_OUT ;
  wire \instance_a/Q2_OUT ;
  wire \instance_a/N_11_i ;
  wire a2c;
  wire clk_top;
  wire \instance_b/Q0_OUT ;
  wire \instance_b/Q1_OUT ;
  wire \instance_b/Q2_OUT ;
  wire \instance_b/Q3_OUT ;
  wire \instance_b/AND4_OUT ;
  wire b2a;
  wire \instance_b/OR4_OUT ;
  wire \instance_b/MODB_OUT ;
  wire modc_clk;
  wire \instance_c/Q0_OUT ;
  wire \instance_c/Q1_OUT ;
  wire \instance_c/Q2_OUT ;
  wire \instance_c/Q3_OUT ;
  wire \instance_c/OR4_OUT ;
  wire \instance_c/C2TOP_OUT ;
  wire \instance_c/AND4_OUT ;
  wire c2and2;
  wire \instance_a/G_7 ;
  wire a2top_obuft_i;
  wire top2a_c_c;
  wire \bufg_modb/IBUFG ;
  wire dll_rst_c;
  wire \instance_a/MODA_OUT ;
  wire \bufg_moda/IBUFG ;
  wire \bufg_modc/IBUFG ;
  wire \instance_c/MODC_OUT ;
  wire b2top_obuft_t;
  wire GLOBAL_LOGIC1;
  wire dll_clk_out;
  wire modb_clk;
  wire b2c;
  wire c2a;
  wire a2b;
  wire GSR = glbl.GSR;
  wire GTS = glbl.GTS;
  wire \dll_1/CLKIN_BUF ;
  wire \dll_1/CLKFB_BUF ;
  wire \dll_1/PSINCDECINVNOT ;
  wire \dll_1/PSENINVNOT ;
  wire \dll_1/PSCLKINVNOT ;
  wire \dll_1/CLK90 ;
  wire \dll_1/CLK180 ;
  wire \dll_1/CLK270 ;
  wire \dll_1/CLK2X ;
  wire \dll_1/CLK2X180 ;
  wire \dll_1/CLKDV ;
  wire \dll_1/CLKFX ;
  wire \dll_1/CLKFX180 ;
  wire \dll_1/LOCKED ;
  wire \dll_1/PSDONE ;
  wire \dll_1/STATUS7 ;
  wire \dll_1/STATUS6 ;
  wire \dll_1/STATUS5 ;
  wire \dll_1/STATUS4 ;
  wire \dll_1/STATUS3 ;
  wire \dll_1/STATUS2 ;
  wire \dll_1/STATUS1 ;
  wire \dll_1/STATUS0 ;
  wire \bufg_modb/BUFG/S_INVNOT ;
  wire \globalclk/S_INVNOT ;
  wire \bufg_modc/BUFG/S_INVNOT ;
  wire \bufg_moda/BUFG/S_INVNOT ;
  wire \instance_a/MODA_OUT/CLKINV ;
  wire \instance_a/MODA_OUT/SRFFMUX ;
  wire \instance_a/MODA_OUT/DYMUX ;
  wire \instance_a/Q0_OUT/CLKINV ;
  wire \instance_a/Q0_OUT/DYMUX ;
  wire \instance_c/Q0_OUT/CLKINV ;
  wire \instance_c/Q0_OUT/DYMUX ;
  wire \instance_c/Q2_OUT/CLKINV ;
  wire \instance_c/Q2_OUT/DYMUX ;
  wire \instance_b/Q0_OUT/CLKINV ;
  wire \instance_b/Q0_OUT/DYMUX ;
  wire \b2c/CLKINV ;
  wire \b2c/DYMUX ;
  wire \instance_a/Q1_OUT/CLKINV ;
  wire \instance_a/Q1_OUT/DYMUX ;
  wire \instance_a/Q2_OUT/CLKINV ;
  wire \instance_a/Q2_OUT/DYMUX ;
  wire \c2a/CLKINV ;
  wire \c2a/DYMUX ;
  wire \b2top_obuft_t/CLKINV ;
  wire \b2top_obuft_t/DYMUX ;
  wire \instance_b/Q1_OUT/CLKINV ;
  wire \instance_b/Q1_OUT/DYMUX ;
  wire \a_and_c/G ;
  wire \instance_a/Q3_OUT/CLKINV ;
  wire \instance_a/Q3_OUT/DYMUX ;
  wire \instance_b/Q2_OUT/CLKINV ;
  wire \instance_b/Q2_OUT/DYMUX ;
  wire \instance_c/Q1_OUT/CLKINV ;
  wire \instance_c/Q1_OUT/DYMUX ;
  wire \instance_c/Q3_OUT/CLKINV ;
  wire \instance_c/Q3_OUT/DYMUX ;
  wire \instance_b/Q3_OUT/CLKINV ;
  wire \instance_b/Q3_OUT/DYMUX ;
  wire \instance_c/MODC_OUT/CLKINV ;
  wire \instance_c/MODC_OUT/DYMUX ;
  wire \a2b/CLKINV ;
  wire \a2b/SRINVNOT ;
  wire \a2b/SRFFMUX ;
  wire \a2b/DYMUX ;
  wire \b2c/FFY/RST ;
  wire \instance_c/Q0_OUT/FFY/RST ;
  wire \instance_a/Q0_OUT/FFY/RST ;
  wire \instance_b/Q1_OUT/FFY/RST ;
  wire \instance_a/Q3_OUT/FFY/RST ;
  wire \instance_b/Q0_OUT/FFY/RST ;
  wire \c2a/FFY/RST ;
  wire \instance_b/Q2_OUT/FFY/RST ;
  wire \instance_a/Q2_OUT/FFY/RST ;
  wire \instance_c/MODC_OUT/FFY/RST ;
  wire \instance_c/Q3_OUT/FFY/RST ;
  wire \instance_c/Q2_OUT/FFY/RST ;
  wire \b2top_obuft_t/FFY/RST ;
  wire \a2c/CLKINV ;
  wire \a2c/SRFFMUX ;
  wire \a2c/G ;
  wire \a2c/DYMUX ;
  wire \b2a/CLKINV ;
  wire \b2a/G ;
  wire \b2a/DYMUX ;
  wire \b2a/F ;
  wire \b2a/DXMUX ;
  wire \b2a/FFX/RST ;
  wire \b2a/FFY/RST ;
  wire \instance_c/C2TOP_OUT/CLKINV ;
  wire \instance_c/C2TOP_OUT/G ;
  wire \instance_c/C2TOP_OUT/DYMUX ;
  wire \instance_c/C2TOP_OUT/FFY/RST ;
  wire \c2and2/CLKINV ;
  wire \c2and2/G ;
  wire \c2and2/DYMUX ;
  wire \c2and2/FFY/RST ;
  wire \a2top_obuft_i/CLKINV ;
  wire \a2top_obuft_i/SRINVNOT ;
  wire \a2top_obuft_i/SRFFMUX ;
  wire \a2top_obuft_i/G ;
  wire \a2top_obuft_i/DYMUX ;
  wire \instance_a/Q1_OUT/FFY/RST ;
  wire \moda_out/O ;
  wire \moda_out/GTS_OR_T ;
  wire \moda_out/ENABLE ;
  wire \modb_out/O ;
  wire \modb_out/GTS_OR_T ;
  wire \modb_out/ENABLE ;
  wire \mod_c_out/O ;
  wire \mod_c_out/GTS_OR_T ;
  wire \mod_c_out/ENABLE ;
  wire \modc_out/O ;
  wire \modc_out/GTS_OR_T ;
  wire \modc_out/ENABLE ;
  wire \obuft_out/T ;
  wire \obuft_out/O ;
  wire \obuft_out/GTS_OR_T ;
  wire \obuft_out/ENABLE ;
  wire \instance_b/Q3_OUT/FFY/RST ;
  wire \instance_c/Q1_OUT/FFY/RST ;
  wire GND;
  wire VCC;
  initial $sdf_annotate("top.sdf");
  X_ONE \GLOBAL_LOGIC1.ONE  (
    .O(GLOBAL_LOGIC1)
  );
  X_BUF ibuf_dll (
    .I(ipad_dll_clk_in),
    .O(\dll_1/CLKIN_BUF )
  );
  X_BUF \dll_1/CLKFB_BUF_0  (
    .I(clk_top),
    .O(\dll_1/CLKFB_BUF )
  );
  defparam dll_1.DUTY_CYCLE_CORRECTION = "TRUE";
  defparam dll_1.CLKDV_DIVIDE = 2.0;
  defparam dll_1.CLKFX_DIVIDE = 1;
  defparam dll_1.CLKFX_MULTIPLY = 4;
  defparam dll_1.CLKOUT_PHASE_SHIFT = "NONE";
  defparam dll_1.CLK_FEEDBACK = "1X";
  defparam dll_1.DLL_FREQUENCY_MODE = "LOW";
  defparam dll_1.PHASE_SHIFT = 0;
  defparam dll_1.MAXPERCLKIN = 41668;
  defparam dll_1.MAXPERPSCLK = 999998999;
  X_DCM dll_1 (
    .CLKIN(\dll_1/CLKIN_BUF ),
    .CLKFB(\dll_1/CLKFB_BUF ),
    .DSSEN(GLOBAL_LOGIC1),
    .RST(dll_rst_c),
    .PSINCDEC(\dll_1/PSINCDECINVNOT ),
    .PSEN(\dll_1/PSENINVNOT ),
    .PSCLK(\dll_1/PSCLKINVNOT ),
    .CLK0(dll_clk_out),
    .CLK90(\dll_1/CLK90 ),
    .CLK180(\dll_1/CLK180 ),
    .CLK270(\dll_1/CLK270 ),
    .CLK2X(\dll_1/CLK2X ),
    .CLK2X180(\dll_1/CLK2X180 ),
    .CLKDV(\dll_1/CLKDV ),
    .CLKFX(\dll_1/CLKFX ),
    .CLKFX180(\dll_1/CLKFX180 ),
    .LOCKED(\dll_1/LOCKED ),
    .PSDONE(\dll_1/PSDONE ),
    .STATUS({\dll_1/STATUS7 , \dll_1/STATUS6 , \dll_1/STATUS5 , \dll_1/STATUS4 , \dll_1/STATUS3 , \dll_1/STATUS2 , \dll_1/STATUS1 , \dll_1/STATUS0 })
  );
  X_INV \dll_1/PSINCDECINV  (
    .I(GLOBAL_LOGIC1),
    .O(\dll_1/PSINCDECINVNOT )
  );
  X_INV \dll_1/PSENINV  (
    .I(GLOBAL_LOGIC1),
    .O(\dll_1/PSENINVNOT )
  );
  X_INV \dll_1/PSCLKINV  (
    .I(GLOBAL_LOGIC1),
    .O(\dll_1/PSCLKINVNOT )
  );
  X_INV \bufg_modb/BUFG/SINV  (
    .I(GLOBAL_LOGIC1),
    .O(\bufg_modb/BUFG/S_INVNOT )
  );
  X_BUFGMUX \bufg_modb/BUFG  (
    .I0(\bufg_modb/IBUFG ),
    .I1(GND),
    .S(\bufg_modb/BUFG/S_INVNOT ),
    .O(modb_clk),
    .GSR(GSR)
  );
  X_INV \globalclk/SINV  (
    .I(GLOBAL_LOGIC1),
    .O(\globalclk/S_INVNOT )
  );
  X_BUFGMUX globalclk (
    .I0(dll_clk_out),
    .I1(GND),
    .S(\globalclk/S_INVNOT ),
    .O(clk_top),
    .GSR(GSR)
  );
  X_INV \bufg_modc/BUFG/SINV  (
    .I(GLOBAL_LOGIC1),
    .O(\bufg_modc/BUFG/S_INVNOT )
  );
  X_BUFGMUX \bufg_modc/BUFG  (
    .I0(\bufg_modc/IBUFG ),
    .I1(GND),
    .S(\bufg_modc/BUFG/S_INVNOT ),
    .O(modc_clk),
    .GSR(GSR)
  );
  X_INV \bufg_moda/BUFG/SINV  (
    .I(GLOBAL_LOGIC1),
    .O(\bufg_moda/BUFG/S_INVNOT )
  );
  X_BUFGMUX \bufg_moda/BUFG  (
    .I0(\bufg_moda/IBUFG ),
    .I1(GND),
    .S(\bufg_moda/BUFG/S_INVNOT ),
    .O(moda_clk),
    .GSR(GSR)
  );
  X_BUF \instance_a/MODA_OUT/CLKINV_1  (
    .I(clk_top),
    .O(\instance_a/MODA_OUT/CLKINV )
  );
  X_BUF \instance_a/MODA_OUT/SRFFMUX_2  (
    .I(\instance_a/Q3_OUT ),
    .O(\instance_a/MODA_OUT/SRFFMUX )
  );
  X_BUF \instance_a/MODA_OUT/DYMUX_3  (
    .I(\instance_a/N_11_i ),
    .O(\instance_a/MODA_OUT/DYMUX )
  );
  X_BUF \instance_a/Q0_OUT/CLKINV_4  (
    .I(clk_top),
    .O(\instance_a/Q0_OUT/CLKINV )
  );
  X_BUF \instance_a/moda_data_ibuf  (
    .I(moda_data),
    .O(\instance_a/Q0_OUT/DYMUX )
  );
  X_BUF \instance_c/Q0_OUT/CLKINV_5  (
    .I(clk_top),
    .O(\instance_c/Q0_OUT/CLKINV )
  );
  X_BUF \instance_c/modc_data_ibuf  (
    .I(modc_data),
    .O(\instance_c/Q0_OUT/DYMUX )
  );
  X_BUF \instance_c/Q2_OUT/CLKINV_6  (
    .I(clk_top),
    .O(\instance_c/Q2_OUT/CLKINV )
  );
  X_BUF \instance_c/Q2_OUT/DYMUX_7  (
    .I(top2a_c_c),
    .O(\instance_c/Q2_OUT/DYMUX )
  );
  X_BUF \instance_b/Q0_OUT/CLKINV_8  (
    .I(clk_top),
    .O(\instance_b/Q0_OUT/CLKINV )
  );
  X_BUF \instance_b/modb_data_ibuf  (
    .I(modb_data),
    .O(\instance_b/Q0_OUT/DYMUX )
  );
  X_BUF \b2c/CLKINV_9  (
    .I(modb_clk),
    .O(\b2c/CLKINV )
  );
  X_BUF \b2c/DYMUX_10  (
    .I(\instance_b/OR4_OUT ),
    .O(\b2c/DYMUX )
  );
  X_BUF \instance_a/Q1_OUT/CLKINV_11  (
    .I(moda_clk),
    .O(\instance_a/Q1_OUT/CLKINV )
  );
  X_BUF \instance_a/Q1_OUT/DYMUX_12  (
    .I(b2a),
    .O(\instance_a/Q1_OUT/DYMUX )
  );
  X_BUF \instance_a/Q2_OUT/CLKINV_13  (
    .I(clk_top),
    .O(\instance_a/Q2_OUT/CLKINV )
  );
  X_BUF \instance_a/Q2_OUT/DYMUX_14  (
    .I(top2a_c_c),
    .O(\instance_a/Q2_OUT/DYMUX )
  );
  X_BUF \c2a/CLKINV_15  (
    .I(modc_clk),
    .O(\c2a/CLKINV )
  );
  X_BUF \c2a/DYMUX_16  (
    .I(\instance_c/AND4_OUT ),
    .O(\c2a/DYMUX )
  );
  X_BUF \b2top_obuft_t/CLKINV_17  (
    .I(modb_clk),
    .O(\b2top_obuft_t/CLKINV )
  );
  X_BUF \b2top_obuft_t/DYMUX_18  (
    .I(\instance_b/AND4_OUT ),
    .O(\b2top_obuft_t/DYMUX )
  );
  X_BUF \instance_b/Q1_OUT/CLKINV_19  (
    .I(modb_clk),
    .O(\instance_b/Q1_OUT/CLKINV )
  );
  X_BUF \instance_b/Q1_OUT/DYMUX_20  (
    .I(a2b),
    .O(\instance_b/Q1_OUT/DYMUX )
  );
  X_BUF \instance_a/Q3_OUT/CLKINV_21  (
    .I(moda_clk),
    .O(\instance_a/Q3_OUT/CLKINV )
  );
  X_BUF \instance_a/Q3_OUT/DYMUX_22  (
    .I(c2a),
    .O(\instance_a/Q3_OUT/DYMUX )
  );
  X_BUF \instance_b/Q2_OUT/CLKINV_23  (
    .I(clk_top),
    .O(\instance_b/Q2_OUT/CLKINV )
  );
  X_BUF \instance_b/top2b_ibuf  (
    .I(top2b),
    .O(\instance_b/Q2_OUT/DYMUX )
  );
  X_BUF \instance_c/Q1_OUT/CLKINV_24  (
    .I(modc_clk),
    .O(\instance_c/Q1_OUT/CLKINV )
  );
  X_BUF \instance_c/Q1_OUT/DYMUX_25  (
    .I(b2c),
    .O(\instance_c/Q1_OUT/DYMUX )
  );
  X_BUF \instance_c/Q3_OUT/CLKINV_26  (
    .I(modc_clk),
    .O(\instance_c/Q3_OUT/CLKINV )
  );
  X_BUF \instance_c/Q3_OUT/DYMUX_27  (
    .I(a2c),
    .O(\instance_c/Q3_OUT/DYMUX )
  );
  X_BUF \instance_b/Q3_OUT/CLKINV_28  (
    .I(modb_clk),
    .O(\instance_b/Q3_OUT/CLKINV )
  );
  X_BUF \instance_b/Q3_OUT/DYMUX_29  (
    .I(\a_and_c/G ),
    .O(\instance_b/Q3_OUT/DYMUX )
  );
  X_BUF \instance_c/MODC_OUT/CLKINV_30  (
    .I(clk_top),
    .O(\instance_c/MODC_OUT/CLKINV )
  );
  X_BUF \instance_c/MODC_OUT/DYMUX_31  (
    .I(\instance_c/OR4_OUT ),
    .O(\instance_c/MODC_OUT/DYMUX )
  );
  X_BUF \a2b/CLKINV_32  (
    .I(clk_top),
    .O(\a2b/CLKINV )
  );
  X_INV \a2b/SRINV  (
    .I(\instance_a/Q3_OUT ),
    .O(\a2b/SRINVNOT )
  );
  X_BUF \a2b/SRFFMUX_33  (
    .I(\a2b/SRINVNOT ),
    .O(\a2b/SRFFMUX )
  );
  X_BUF \a2b/DYMUX_34  (
    .I(\instance_a/G_7 ),
    .O(\a2b/DYMUX )
  );
  X_IPAD \moda_data/PAD  (
    .PAD(moda_data)
  );
  X_IPAD \modc_data/PAD  (
    .PAD(modc_data)
  );
  X_BUF \b2c/FFY/RSTOR  (
    .I(GSR),
    .O(\b2c/FFY/RST )
  );
  X_FF \instance_b/B2C_OUT  (
    .I(\b2c/DYMUX ),
    .CE(VCC),
    .CLK(\b2c/CLKINV ),
    .SET(GND),
    .RST(\b2c/FFY/RST ),
    .O(b2c)
  );
  X_SFF \instance_a/MODA_OUT_35  (
    .I(\instance_a/MODA_OUT/DYMUX ),
    .CE(VCC),
    .CLK(\instance_a/MODA_OUT/CLKINV ),
    .SET(GSR),
    .RST(GND),
    .SSET(\instance_a/MODA_OUT/SRFFMUX ),
    .SRST(GND),
    .O(\instance_a/MODA_OUT )
  );
  X_BUF \instance_c/Q0_OUT/FFY/RSTOR  (
    .I(GSR),
    .O(\instance_c/Q0_OUT/FFY/RST )
  );
  X_FF \instance_c/Q0_OUT_reg  (
    .I(\instance_c/Q0_OUT/DYMUX ),
    .CE(VCC),
    .CLK(\instance_c/Q0_OUT/CLKINV ),
    .SET(GND),
    .RST(\instance_c/Q0_OUT/FFY/RST ),
    .O(\instance_c/Q0_OUT )
  );
  X_SFF \instance_a/A2B_OUT  (
    .I(\a2b/DYMUX ),
    .CE(VCC),
    .CLK(\a2b/CLKINV ),
    .SET(GND),
    .RST(GSR),
    .SSET(GND),
    .SRST(\a2b/SRFFMUX ),
    .O(a2b)
  );
  X_BUF \instance_a/Q0_OUT/FFY/RSTOR  (
    .I(GSR),
    .O(\instance_a/Q0_OUT/FFY/RST )
  );
  X_FF \instance_a/Q0_OUT_36  (
    .I(\instance_a/Q0_OUT/DYMUX ),
    .CE(VCC),
    .CLK(\instance_a/Q0_OUT/CLKINV ),
    .SET(GND),
    .RST(\instance_a/Q0_OUT/FFY/RST ),
    .O(\instance_a/Q0_OUT )