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FPGA-CPLD_DesignTool(8-9-10)源代码

    );
  b2a_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => b2a_G,
      O => instance_b_OR4_OUT
    );
  b2a_DYMUX_46 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_b_OR4_OUT,
      O => b2a_DYMUX
    );
  b2a_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => b2a_F,
      O => instance_b_AND4_OUT
    );
  b2a_DXMUX_47 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_b_AND4_OUT,
      O => b2a_DXMUX
    );
  b2a_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => b2a_FFX_RST
    );
  instance_b_B2A_OUT : X_FF
    port map (
      I => b2a_DXMUX,
      CE => VCC,
      CLK => b2a_CLKINV,
      SET => GND,
      RST => b2a_FFX_RST,
      O => b2a
    );
  b2a_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => b2a_FFY_RST
    );
  instance_b_MODB_OUT_48 : X_FF
    port map (
      I => b2a_DYMUX,
      CE => VCC,
      CLK => b2a_CLKINV,
      SET => GND,
      RST => b2a_FFY_RST,
      O => instance_b_MODB_OUT
    );
  instance_b_OR4_OUT1 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => instance_b_Q2_OUT,
      ADR1 => instance_b_Q3_OUT,
      ADR2 => instance_b_Q0_OUT,
      ADR3 => instance_b_Q1_OUT,
      O => b2a_G
    );
  instance_b_AND4_OUT1 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => instance_b_Q0_OUT,
      ADR1 => instance_b_Q1_OUT,
      ADR2 => instance_b_Q2_OUT,
      ADR3 => instance_b_Q3_OUT,
      O => b2a_F
    );
  instance_c_C2TOP_OUT_CLKINV_49 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modc_clk,
      O => instance_c_C2TOP_OUT_CLKINV
    );
  instance_c_C2TOP_OUT_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_c_C2TOP_OUT_G,
      O => instance_c_OR4_OUT
    );
  instance_c_C2TOP_OUT_DYMUX_50 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_c_OR4_OUT,
      O => instance_c_C2TOP_OUT_DYMUX
    );
  instance_c_C19 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => instance_c_Q0_OUT,
      ADR1 => instance_c_Q1_OUT,
      ADR2 => instance_c_Q2_OUT,
      ADR3 => instance_c_Q3_OUT,
      O => instance_c_C2TOP_OUT_G
    );
  instance_c_C2TOP_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_c_C2TOP_OUT_FFY_RST
    );
  instance_c_C2TOP_OUT_reg : X_FF
    port map (
      I => instance_c_C2TOP_OUT_DYMUX,
      CE => VCC,
      CLK => instance_c_C2TOP_OUT_CLKINV,
      SET => GND,
      RST => instance_c_C2TOP_OUT_FFY_RST,
      O => instance_c_C2TOP_OUT
    );
  c2and2_CLKINV_51 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => clk_top,
      O => c2and2_CLKINV
    );
  c2and2_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => c2and2_G,
      O => instance_c_AND4_OUT
    );
  c2and2_DYMUX_52 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_c_AND4_OUT,
      O => c2and2_DYMUX
    );
  c2and2_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => c2and2_FFY_RST
    );
  instance_c_C2AND2_OUT_reg : X_FF
    port map (
      I => c2and2_DYMUX,
      CE => VCC,
      CLK => c2and2_CLKINV,
      SET => GND,
      RST => c2and2_FFY_RST,
      O => c2and2
    );
  instance_c_C18 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => instance_c_Q0_OUT,
      ADR1 => instance_c_Q1_OUT,
      ADR2 => instance_c_Q2_OUT,
      ADR3 => instance_c_Q3_OUT,
      O => c2and2_G
    );
  a2top_obuft_i_CLKINV_53 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => moda_clk,
      O => a2top_obuft_i_CLKINV
    );
  a2top_obuft_i_SRINV : X_INV
    port map (
      I => instance_a_Q3_OUT,
      O => a2top_obuft_i_SRINVNOT
    );
  a2top_obuft_i_SRFFMUX_54 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => a2top_obuft_i_SRINVNOT,
      O => a2top_obuft_i_SRFFMUX
    );
  a2top_obuft_i_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => a2top_obuft_i_G,
      O => instance_a_G_7
    );
  a2top_obuft_i_DYMUX_55 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_a_G_7,
      O => a2top_obuft_i_DYMUX
    );
  instance_a_G_7_56 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => instance_a_Q0_OUT,
      ADR1 => instance_a_Q1_OUT,
      ADR2 => instance_a_Q2_OUT,
      ADR3 => VCC,
      O => a2top_obuft_i_G
    );
  instance_a_A2TOP_OBUFT_I_OUT : X_SFF
    port map (
      I => a2top_obuft_i_DYMUX,
      CE => VCC,
      CLK => a2top_obuft_i_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => a2top_obuft_i_SRFFMUX,
      O => a2top_obuft_i
    );
  instance_a_Q1_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_a_Q1_OUT_FFY_RST
    );
  instance_a_Q1_OUT_57 : X_FF
    port map (
      I => instance_a_Q1_OUT_DYMUX,
      CE => VCC,
      CLK => instance_a_Q1_OUT_CLKINV,
      SET => GND,
      RST => instance_a_Q1_OUT_FFY_RST,
      O => instance_a_Q1_OUT
    );
  moda_out_GTS_OR_T_58 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => moda_out_GTS_OR_T
    );
  moda_out_ENABLEINV : X_INV
    port map (
      I => moda_out_GTS_OR_T,
      O => moda_out_ENABLE
    );
  instance_a_moda_out_obuf : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => moda_out_O,
      CTL => moda_out_ENABLE,
      O => moda_out
    );
  modb_out_GTS_OR_T_59 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => modb_out_GTS_OR_T
    );
  modb_out_ENABLEINV : X_INV
    port map (
      I => modb_out_GTS_OR_T,
      O => modb_out_ENABLE
    );
  instance_b_modb_out_obuf : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modb_out_O,
      CTL => modb_out_ENABLE,
      O => modb_out
    );
  mod_c_out_GTS_OR_T_60 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => mod_c_out_GTS_OR_T
    );
  mod_c_out_ENABLEINV : X_INV
    port map (
      I => mod_c_out_GTS_OR_T,
      O => mod_c_out_ENABLE
    );
  instance_c_mod_c_out_obuf : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => mod_c_out_O,
      CTL => mod_c_out_ENABLE,
      O => mod_c_out
    );
  modc_out_GTS_OR_T_61 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GTS,
      O => modc_out_GTS_OR_T
    );
  modc_out_ENABLEINV : X_INV
    port map (
      I => modc_out_GTS_OR_T,
      O => modc_out_ENABLE
    );
  instance_c_modc_out_obuf : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modc_out_O,
      CTL => modc_out_ENABLE,
      O => modc_out
    );
  obuft_out_GTS_OR_T_62 : X_OR2
    port map (
      I0 => GTS,
      I1 => obuft_out_T,
      O => obuft_out_GTS_OR_T
    );
  obuft_out_ENABLEINV : X_INV
    port map (
      I => obuft_out_GTS_OR_T,
      O => obuft_out_ENABLE
    );
  obuft_out_obuft : X_TRI_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => obuft_out_O,
      CTL => obuft_out_ENABLE,
      O => obuft_out
    );
  instance_b_Q3_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_b_Q3_OUT_FFY_RST
    );
  instance_b_Q3_OUT_63 : X_FF
    port map (
      I => instance_b_Q3_OUT_DYMUX,
      CE => VCC,
      CLK => instance_b_Q3_OUT_CLKINV,
      SET => GND,
      RST => instance_b_Q3_OUT_FFY_RST,
      O => instance_b_Q3_OUT
    );
  instance_c_Q1_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_c_Q1_OUT_FFY_RST
    );
  instance_c_Q1_OUT_reg : X_FF
    port map (
      I => instance_c_Q1_OUT_DYMUX,
      CE => VCC,
      CLK => instance_c_Q1_OUT_CLKINV,
      SET => GND,
      RST => instance_c_Q1_OUT_FFY_RST,
      O => instance_c_Q1_OUT
    );
  top2a_c_ibuf : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => top2a_c,
      O => top2a_c_c
    );
  bufg_modb_IBUFG_64 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modb_clk_pad,
      O => bufg_modb_IBUFG
    );
  dll_rst_ibuf : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => dll_rst,
      O => dll_rst_c
    );
  moda_out_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_a_MODA_OUT,
      O => moda_out_O
    );
  modb_out_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_b_MODB_OUT,
      O => modb_out_O
    );
  mod_c_out_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_c_C2TOP_OUT,
      O => mod_c_out_O
    );
  bufg_moda_IBUFG_65 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => moda_clk_pad,
      O => bufg_moda_IBUFG
    );
  bufg_modc_IBUFG_66 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modc_clk_pad,
      O => bufg_modc_IBUFG
    );
  modc_out_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_c_MODC_OUT,
      O => modc_out_O
    );
  obuft_out_OUTPUT_TFF_TMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => b2top_obuft_t,
      O => obuft_out_T
    );
  obuft_out_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => a2top_obuft_i,
      O => obuft_out_O
    );
  NlwBlock_top_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_top_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : ROC     port map (O => GSR);
  NlwBlockTOC : TOC     port map (O => GTS);
end STRUCTURE;