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FPGA-CPLD_DesignTool(8-9-10)源代码

    );
  instance_a_Q1_OUT_DYMUX_12 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => b2a,
      O => instance_a_Q1_OUT_DYMUX
    );
  instance_a_Q2_OUT_CLKINV_13 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => clk_top,
      O => instance_a_Q2_OUT_CLKINV
    );
  instance_a_Q2_OUT_DYMUX_14 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => top2a_c_c,
      O => instance_a_Q2_OUT_DYMUX
    );
  c2a_CLKINV_15 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modc_clk,
      O => c2a_CLKINV
    );
  c2a_DYMUX_16 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_c_AND4_OUT,
      O => c2a_DYMUX
    );
  b2top_obuft_t_CLKINV_17 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modb_clk,
      O => b2top_obuft_t_CLKINV
    );
  b2top_obuft_t_DYMUX_18 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_b_AND4_OUT,
      O => b2top_obuft_t_DYMUX
    );
  instance_b_Q1_OUT_CLKINV_19 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modb_clk,
      O => instance_b_Q1_OUT_CLKINV
    );
  instance_b_Q1_OUT_DYMUX_20 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => a2b,
      O => instance_b_Q1_OUT_DYMUX
    );
  instance_a_Q3_OUT_CLKINV_21 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => moda_clk,
      O => instance_a_Q3_OUT_CLKINV
    );
  instance_a_Q3_OUT_DYMUX_22 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => c2a,
      O => instance_a_Q3_OUT_DYMUX
    );
  instance_b_Q2_OUT_CLKINV_23 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => clk_top,
      O => instance_b_Q2_OUT_CLKINV
    );
  instance_b_top2b_ibuf : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => top2b,
      O => instance_b_Q2_OUT_DYMUX
    );
  instance_c_Q1_OUT_CLKINV_24 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modc_clk,
      O => instance_c_Q1_OUT_CLKINV
    );
  instance_c_Q1_OUT_DYMUX_25 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => b2c,
      O => instance_c_Q1_OUT_DYMUX
    );
  instance_c_Q3_OUT_CLKINV_26 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modc_clk,
      O => instance_c_Q3_OUT_CLKINV
    );
  instance_c_Q3_OUT_DYMUX_27 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => a2c,
      O => instance_c_Q3_OUT_DYMUX
    );
  instance_b_Q3_OUT_CLKINV_28 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => modb_clk,
      O => instance_b_Q3_OUT_CLKINV
    );
  instance_b_Q3_OUT_DYMUX_29 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => a_and_c_G,
      O => instance_b_Q3_OUT_DYMUX
    );
  instance_c_MODC_OUT_CLKINV_30 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => clk_top,
      O => instance_c_MODC_OUT_CLKINV
    );
  instance_c_MODC_OUT_DYMUX_31 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_c_OR4_OUT,
      O => instance_c_MODC_OUT_DYMUX
    );
  a2b_CLKINV_32 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => clk_top,
      O => a2b_CLKINV
    );
  a2b_SRINV : X_INV
    port map (
      I => instance_a_Q3_OUT,
      O => a2b_SRINVNOT
    );
  a2b_SRFFMUX_33 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => a2b_SRINVNOT,
      O => a2b_SRFFMUX
    );
  a2b_DYMUX_34 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_a_G_7,
      O => a2b_DYMUX
    );
  b2c_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => b2c_FFY_RST
    );
  instance_b_B2C_OUT : X_FF
    port map (
      I => b2c_DYMUX,
      CE => VCC,
      CLK => b2c_CLKINV,
      SET => GND,
      RST => b2c_FFY_RST,
      O => b2c
    );
  instance_a_MODA_OUT_35 : X_SFF
    port map (
      I => instance_a_MODA_OUT_DYMUX,
      CE => VCC,
      CLK => instance_a_MODA_OUT_CLKINV,
      SET => GSR,
      RST => GND,
      SSET => instance_a_MODA_OUT_SRFFMUX,
      SRST => GND,
      O => instance_a_MODA_OUT
    );
  instance_c_Q0_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_c_Q0_OUT_FFY_RST
    );
  instance_c_Q0_OUT_reg : X_FF
    port map (
      I => instance_c_Q0_OUT_DYMUX,
      CE => VCC,
      CLK => instance_c_Q0_OUT_CLKINV,
      SET => GND,
      RST => instance_c_Q0_OUT_FFY_RST,
      O => instance_c_Q0_OUT
    );
  instance_a_A2B_OUT : X_SFF
    port map (
      I => a2b_DYMUX,
      CE => VCC,
      CLK => a2b_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => a2b_SRFFMUX,
      O => a2b
    );
  instance_a_Q0_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_a_Q0_OUT_FFY_RST
    );
  instance_a_Q0_OUT_36 : X_FF
    port map (
      I => instance_a_Q0_OUT_DYMUX,
      CE => VCC,
      CLK => instance_a_Q0_OUT_CLKINV,
      SET => GND,
      RST => instance_a_Q0_OUT_FFY_RST,
      O => instance_a_Q0_OUT
    );
  instance_b_Q1_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_b_Q1_OUT_FFY_RST
    );
  instance_b_Q1_OUT_37 : X_FF
    port map (
      I => instance_b_Q1_OUT_DYMUX,
      CE => VCC,
      CLK => instance_b_Q1_OUT_CLKINV,
      SET => GND,
      RST => instance_b_Q1_OUT_FFY_RST,
      O => instance_b_Q1_OUT
    );
  instance_a_Q3_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_a_Q3_OUT_FFY_RST
    );
  instance_a_Q3_OUT_38 : X_FF
    port map (
      I => instance_a_Q3_OUT_DYMUX,
      CE => VCC,
      CLK => instance_a_Q3_OUT_CLKINV,
      SET => GND,
      RST => instance_a_Q3_OUT_FFY_RST,
      O => instance_a_Q3_OUT
    );
  instance_b_Q0_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_b_Q0_OUT_FFY_RST
    );
  instance_b_Q0_OUT_39 : X_FF
    port map (
      I => instance_b_Q0_OUT_DYMUX,
      CE => VCC,
      CLK => instance_b_Q0_OUT_CLKINV,
      SET => GND,
      RST => instance_b_Q0_OUT_FFY_RST,
      O => instance_b_Q0_OUT
    );
  c2a_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => c2a_FFY_RST
    );
  instance_c_C2A_OUT_reg : X_FF
    port map (
      I => c2a_DYMUX,
      CE => VCC,
      CLK => c2a_CLKINV,
      SET => GND,
      RST => c2a_FFY_RST,
      O => c2a
    );
  instance_b_Q2_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_b_Q2_OUT_FFY_RST
    );
  instance_b_Q2_OUT_40 : X_FF
    port map (
      I => instance_b_Q2_OUT_DYMUX,
      CE => VCC,
      CLK => instance_b_Q2_OUT_CLKINV,
      SET => GND,
      RST => instance_b_Q2_OUT_FFY_RST,
      O => instance_b_Q2_OUT
    );
  a_and_c : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => b2a,
      ADR1 => c2and2,
      ADR2 => VCC,
      ADR3 => VCC,
      O => a_and_c_G
    );
  instance_a_Q2_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_a_Q2_OUT_FFY_RST
    );
  instance_a_Q2_OUT_41 : X_FF
    port map (
      I => instance_a_Q2_OUT_DYMUX,
      CE => VCC,
      CLK => instance_a_Q2_OUT_CLKINV,
      SET => GND,
      RST => instance_a_Q2_OUT_FFY_RST,
      O => instance_a_Q2_OUT
    );
  instance_c_MODC_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_c_MODC_OUT_FFY_RST
    );
  instance_c_MODC_OUT_reg : X_FF
    port map (
      I => instance_c_MODC_OUT_DYMUX,
      CE => VCC,
      CLK => instance_c_MODC_OUT_CLKINV,
      SET => GND,
      RST => instance_c_MODC_OUT_FFY_RST,
      O => instance_c_MODC_OUT
    );
  instance_c_Q3_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_c_Q3_OUT_FFY_RST
    );
  instance_c_Q3_OUT_reg : X_FF
    port map (
      I => instance_c_Q3_OUT_DYMUX,
      CE => VCC,
      CLK => instance_c_Q3_OUT_CLKINV,
      SET => GND,
      RST => instance_c_Q3_OUT_FFY_RST,
      O => instance_c_Q3_OUT
    );
  instance_c_Q2_OUT_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => instance_c_Q2_OUT_FFY_RST
    );
  instance_c_Q2_OUT_reg : X_FF
    port map (
      I => instance_c_Q2_OUT_DYMUX,
      CE => VCC,
      CLK => instance_c_Q2_OUT_CLKINV,
      SET => GND,
      RST => instance_c_Q2_OUT_FFY_RST,
      O => instance_c_Q2_OUT
    );
  b2top_obuft_t_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => GSR,
      O => b2top_obuft_t_FFY_RST
    );
  instance_b_B2TOP_OBUFT_T_OUT : X_FF
    port map (
      I => b2top_obuft_t_DYMUX,
      CE => VCC,
      CLK => b2top_obuft_t_CLKINV,
      SET => GND,
      RST => b2top_obuft_t_FFY_RST,
      O => b2top_obuft_t
    );
  a2c_CLKINV_42 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => moda_clk,
      O => a2c_CLKINV
    );
  a2c_SRFFMUX_43 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_a_Q3_OUT,
      O => a2c_SRFFMUX
    );
  a2c_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => a2c_G,
      O => instance_a_N_11_i
    );
  a2c_DYMUX_44 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => instance_a_N_11_i,
      O => a2c_DYMUX
    );
  instance_a_A2C_OUT : X_SFF
    port map (
      I => a2c_DYMUX,
      CE => VCC,
      CLK => a2c_CLKINV,
      SET => GSR,
      RST => GND,
      SSET => a2c_SRFFMUX,
      SRST => GND,
      O => a2c
    );
  instance_a_N_12_i : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => instance_a_Q0_OUT,
      ADR1 => instance_a_Q1_OUT,
      ADR2 => instance_a_Q2_OUT,
      ADR3 => VCC,
      O => a2c_G
    );
  b2a_CLKINV_45 : X_BUF_PP
    generic map(
      PATHPULSE => 665 ps
    )
    port map (
      I => clk_top,
      O => b2a_CLKINV