xst_module_b.npl

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· NPL 代码 · 共 22 行

JDF F
// Created by Project Navigator ver 1.0
PROJECT XST_module_b
DESIGN xst_module_b Normal
DEVFAM virtex2
DEVFAMTIME 0
DEVICE xc2v40
DEVICETIME 1048681196
DEVPKG cs144
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
FLOW XST Verilog
FLOWTIME 0
MODULE ..\module_b.v
MODSTYLE module_b Normal
[Normal]
p_xstPackIORegister=xstvlg, virtex2, Verilog.t_synthesize, 1048681445, No
xilxSynthAddIObuf=xstvlg, virtex2, Verilog.t_synthesize, 1048681445, False
[STRATEGY-LIST]
Normal=True