module_a.ncf

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· NCF 代码 · 共 20 行

#
# Constraints generated by Synplify Pro 7.2, Build 175R
#

# Period Constraints

#Begin clock constraints
NET "MODA_CLK" TNM_NET = "MODA_CLK"; 
TIMESPEC "TS_MODA_CLK" = PERIOD "MODA_CLK" 10.000 ns HIGH 50.00%; 
NET "CLK_TOP" TNM_NET = "CLK_TOP"; 
TIMESPEC "TS_CLK_TOP" = PERIOD "CLK_TOP" "TS_MODA_CLK" * 1.000000 HIGH 50.00%; 
#End clock constraints

# Output Constraints
# Input Constraints

# Location Constraints

# End of generated constraints