module_c.out

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· OUT 代码 · 共 68 行

Inferred memory devices in process 'TOP_CLK'
	in routine module_c line 23 in
         file 'J:/Example-8-1/Modular_Design/syn_modules/module_c/module_c.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|   C2AND2_OUT_reg    | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|    MODC_OUT_reg     | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|     Q0_OUT_reg      | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|     Q2_OUT_reg      | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
===============================================================================

C2AND2_OUT_reg
--------------
    set/reset/toggle: none


MODC_OUT_reg
------------
    set/reset/toggle: none


Q0_OUT_reg
----------
    set/reset/toggle: none


Q2_OUT_reg
----------
    set/reset/toggle: none



Inferred memory devices in process 'CLK_MODA'
	in routine module_c line 30 in
         file 'J:/Example-8-1/Modular_Design/syn_modules/module_c/module_c.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     C2A_OUT_reg     | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|    C2TOP_OUT_reg    | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|     Q1_OUT_reg      | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
|     Q3_OUT_reg      | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
===============================================================================

C2A_OUT_reg
-----------
    set/reset/toggle: none


C2TOP_OUT_reg
-------------
    set/reset/toggle: none


Q1_OUT_reg
----------
    set/reset/toggle: none


Q3_OUT_reg
----------
    set/reset/toggle: none


Writing to hnl file 'J:\Example-8-1\Modular_Design\syn_modules\module_c/FE_module_c/workdirs/WORK/module_c.hnl'