top.plg

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· PLG 代码 · 共 12 行

@P:  Worst Slack : 994.509
@P:  System - Estimated Frequency : 182.1 MHz
@P:  System - Requested Frequency : 1.0 MHz
@P:  System - Estimated Period : 5.491
@P:  System - Requested Period : 1000.000
@P:  System - Slack : 994.509
@P: top Part : xc2v40cs144-5
@P: top I/O primitives : 12
@P: top I/O Register bits : 0
@P: top Register bits (Non I/O) : 0 (0%)
@P: top Total Luts : 1 (0%)