synpro_top.prd

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· PRD 代码 · 共 14 行

#-- Synplicity, Inc.
#-- Version 7.2        
#-- Project file J:\Example-8-1\Modular_Design\syn_top\SynPro_top.prd
#-- Written on Wed Mar 26 20:44:26 2003

#
### Watch Implementation type ###
#
watch_impl -active
#
### Watch Implementation properties ###
#
watch_prop -clear